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72062f5744
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.
This initial commit should have support for:
+ Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
(except the late addition CRC instructions).
+ CodeGen features required for C++03 and C99.
+ Compilation for the "small" memory model: code+static data <
4GB.
+ Absolute and position-independent code.
+ GNU-style (i.e. "__thread") TLS.
+ Debugging information.
The principal omission, currently, is performance tuning.
This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.
Further reviews would be gratefully received.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
109 lines
3.1 KiB
C++
109 lines
3.1 KiB
C++
//=- AArch64/AArch64FixupKinds.h - AArch64 Specific Fixup Entries -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_AARCH64_AARCH64FIXUPKINDS_H
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#define LLVM_AARCH64_AARCH64FIXUPKINDS_H
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#include "llvm/MC/MCFixup.h"
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namespace llvm {
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namespace AArch64 {
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enum Fixups {
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fixup_a64_ld_prel = FirstTargetFixupKind,
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fixup_a64_adr_prel,
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fixup_a64_adr_prel_page,
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fixup_a64_add_lo12,
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fixup_a64_ldst8_lo12,
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fixup_a64_ldst16_lo12,
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fixup_a64_ldst32_lo12,
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fixup_a64_ldst64_lo12,
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fixup_a64_ldst128_lo12,
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fixup_a64_tstbr,
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fixup_a64_condbr,
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fixup_a64_uncondbr,
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fixup_a64_call,
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fixup_a64_movw_uabs_g0,
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fixup_a64_movw_uabs_g0_nc,
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fixup_a64_movw_uabs_g1,
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fixup_a64_movw_uabs_g1_nc,
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fixup_a64_movw_uabs_g2,
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fixup_a64_movw_uabs_g2_nc,
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fixup_a64_movw_uabs_g3,
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fixup_a64_movw_sabs_g0,
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fixup_a64_movw_sabs_g1,
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fixup_a64_movw_sabs_g2,
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fixup_a64_adr_prel_got_page,
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fixup_a64_ld64_got_lo12_nc,
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// Produce offsets relative to the module's dynamic TLS area.
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fixup_a64_movw_dtprel_g2,
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fixup_a64_movw_dtprel_g1,
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fixup_a64_movw_dtprel_g1_nc,
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fixup_a64_movw_dtprel_g0,
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fixup_a64_movw_dtprel_g0_nc,
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fixup_a64_add_dtprel_hi12,
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fixup_a64_add_dtprel_lo12,
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fixup_a64_add_dtprel_lo12_nc,
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fixup_a64_ldst8_dtprel_lo12,
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fixup_a64_ldst8_dtprel_lo12_nc,
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fixup_a64_ldst16_dtprel_lo12,
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fixup_a64_ldst16_dtprel_lo12_nc,
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fixup_a64_ldst32_dtprel_lo12,
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fixup_a64_ldst32_dtprel_lo12_nc,
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fixup_a64_ldst64_dtprel_lo12,
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fixup_a64_ldst64_dtprel_lo12_nc,
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// Produce the GOT entry containing a variable's address in TLS's
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// initial-exec mode.
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fixup_a64_movw_gottprel_g1,
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fixup_a64_movw_gottprel_g0_nc,
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fixup_a64_adr_gottprel_page,
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fixup_a64_ld64_gottprel_lo12_nc,
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fixup_a64_ld_gottprel_prel19,
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// Produce offsets relative to the thread pointer: TPIDR_EL0.
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fixup_a64_movw_tprel_g2,
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fixup_a64_movw_tprel_g1,
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fixup_a64_movw_tprel_g1_nc,
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fixup_a64_movw_tprel_g0,
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fixup_a64_movw_tprel_g0_nc,
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fixup_a64_add_tprel_hi12,
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fixup_a64_add_tprel_lo12,
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fixup_a64_add_tprel_lo12_nc,
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fixup_a64_ldst8_tprel_lo12,
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fixup_a64_ldst8_tprel_lo12_nc,
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fixup_a64_ldst16_tprel_lo12,
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fixup_a64_ldst16_tprel_lo12_nc,
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fixup_a64_ldst32_tprel_lo12,
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fixup_a64_ldst32_tprel_lo12_nc,
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fixup_a64_ldst64_tprel_lo12,
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fixup_a64_ldst64_tprel_lo12_nc,
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// Produce the special fixups used by the general-dynamic TLS model.
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fixup_a64_tlsdesc_adr_page,
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fixup_a64_tlsdesc_ld64_lo12_nc,
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fixup_a64_tlsdesc_add_lo12_nc,
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fixup_a64_tlsdesc_call,
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// Marker
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LastTargetFixupKind,
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NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
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};
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}
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}
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#endif
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