mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-04 22:07:27 +00:00
fdc834046e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86423 91177308-0d34-0410-b5e6-96231b3b80d8
106 lines
2.8 KiB
C++
106 lines
2.8 KiB
C++
//===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the ARM implementation of the TargetInstrInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "ARMInstrInfo.h"
|
|
#include "ARM.h"
|
|
#include "ARMAddressingModes.h"
|
|
#include "ARMGenInstrInfo.inc"
|
|
#include "ARMMachineFunctionInfo.h"
|
|
#include "llvm/ADT/STLExtras.h"
|
|
#include "llvm/CodeGen/LiveVariables.h"
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
|
#include "llvm/CodeGen/MachineJumpTableInfo.h"
|
|
#include "llvm/MC/MCAsmInfo.h"
|
|
using namespace llvm;
|
|
|
|
ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
|
|
: ARMBaseInstrInfo(STI), RI(*this, STI) {
|
|
}
|
|
|
|
unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
|
|
switch (Opc) {
|
|
default: break;
|
|
case ARM::LDR_PRE:
|
|
case ARM::LDR_POST:
|
|
return ARM::LDR;
|
|
case ARM::LDRH_PRE:
|
|
case ARM::LDRH_POST:
|
|
return ARM::LDRH;
|
|
case ARM::LDRB_PRE:
|
|
case ARM::LDRB_POST:
|
|
return ARM::LDRB;
|
|
case ARM::LDRSH_PRE:
|
|
case ARM::LDRSH_POST:
|
|
return ARM::LDRSH;
|
|
case ARM::LDRSB_PRE:
|
|
case ARM::LDRSB_POST:
|
|
return ARM::LDRSB;
|
|
case ARM::STR_PRE:
|
|
case ARM::STR_POST:
|
|
return ARM::STR;
|
|
case ARM::STRH_PRE:
|
|
case ARM::STRH_POST:
|
|
return ARM::STRH;
|
|
case ARM::STRB_PRE:
|
|
case ARM::STRB_POST:
|
|
return ARM::STRB;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
|
|
if (MBB.empty()) return false;
|
|
|
|
switch (MBB.back().getOpcode()) {
|
|
case ARM::BX_RET: // Return.
|
|
case ARM::LDM_RET:
|
|
case ARM::B:
|
|
case ARM::BRIND:
|
|
case ARM::BR_JTr: // Jumptable branch.
|
|
case ARM::BR_JTm: // Jumptable branch through mem.
|
|
case ARM::BR_JTadd: // Jumptable branch add to pc.
|
|
return true;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
void ARMInstrInfo::
|
|
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
unsigned DestReg, unsigned SubIdx,
|
|
const MachineInstr *Orig) const {
|
|
DebugLoc dl = Orig->getDebugLoc();
|
|
unsigned Opcode = Orig->getOpcode();
|
|
switch (Opcode) {
|
|
default:
|
|
break;
|
|
case ARM::MOVi2pieces: {
|
|
RI.emitLoadConstPool(MBB, I, dl,
|
|
DestReg, SubIdx,
|
|
Orig->getOperand(1).getImm(),
|
|
(ARMCC::CondCodes)Orig->getOperand(2).getImm(),
|
|
Orig->getOperand(3).getReg());
|
|
MachineInstr *NewMI = prior(I);
|
|
NewMI->getOperand(0).setSubReg(SubIdx);
|
|
return;
|
|
}
|
|
}
|
|
|
|
return ARMBaseInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig);
|
|
}
|
|
|