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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129311 91177308-0d34-0410-b5e6-96231b3b80d8
205 lines
6.8 KiB
TableGen
205 lines
6.8 KiB
TableGen
//===- MBlazeInstrFormats.td - MB Instruction defs ---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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class Format<bits<6> val> {
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bits<6> Value = val;
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}
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def FPseudo : Format<0>;
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def FRRR : Format<1>; // ADD, OR, etc.
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def FRRI : Format<2>; // ADDI, ORI, etc.
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def FCRR : Format<3>; // PUTD, WDC, WIC, BEQ, BNE, BGE, etc.
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def FCRI : Format<4>; // RTID, RTED, RTSD, BEQI, BNEI, BGEI, etc.
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def FRCR : Format<5>; // BRLD, BRALD, GETD
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def FRCI : Format<6>; // BRLID, BRALID, MSRCLR, MSRSET
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def FCCR : Format<7>; // BR, BRA, BRD, etc.
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def FCCI : Format<8>; // IMM, BRI, BRAI, BRID, etc.
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def FRRCI : Format<9>; // BSRLI, BSRAI, BSLLI
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def FRRC : Format<10>; // SEXT8, SEXT16, SRA, SRC, SRL, FLT, FINT, FSQRT
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def FRCX : Format<11>; // GET
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def FRCS : Format<12>; // MFS
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def FCRCS : Format<13>; // MTS
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def FCRCX : Format<14>; // PUT
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def FCX : Format<15>; // TPUT
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def FCR : Format<16>; // TPUTD
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def FRIR : Format<17>; // RSUBI
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def FRRRR : Format<18>; // RSUB, FRSUB
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def FRI : Format<19>; // RSUB, FRSUB
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def FC : Format<20>; // NOP
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//===----------------------------------------------------------------------===//
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// Describe MBlaze instructions format
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//
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// CPU INSTRUCTION FORMATS
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//
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// opcode - operation code.
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// rd - dst reg.
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// ra - first src. reg.
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// rb - second src. reg.
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// imm16 - 16-bit immediate value.
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//
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//===----------------------------------------------------------------------===//
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// Generic MBlaze Format
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class MBlazeInst<bits<6> op, Format form, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin> : Instruction {
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let Namespace = "MBlaze";
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field bits<32> Inst;
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bits<6> opcode = op;
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Format Form = form;
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bits<6> FormBits = Form.Value;
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// Top 6 bits are the 'opcode' field
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let Inst{0-5} = opcode;
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// If the instruction is marked as a pseudo, set isCodeGenOnly so that the
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// assembler and disassmbler ignore it.
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let isCodeGenOnly = !eq(!cast<string>(form), "FPseudo");
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Itinerary = itin;
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// TSFlags layout should be kept in sync with MBlazeInstrInfo.h.
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let TSFlags{5-0} = FormBits;
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}
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//===----------------------------------------------------------------------===//
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// Pseudo instruction class
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//===----------------------------------------------------------------------===//
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class MBlazePseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
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MBlazeInst<0x0, FPseudo, outs, ins, asmstr, pattern, IIC_Pseudo>;
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//===----------------------------------------------------------------------===//
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// Type A instruction class in MBlaze : <|opcode|rd|ra|rb|flags|>
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//===----------------------------------------------------------------------===//
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class TA<bits<6> op, bits<11> flags, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<op,FRRR,outs, ins, asmstr, pattern, itin>
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{
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bits<5> rd;
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bits<5> ra;
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bits<5> rb;
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let Inst{6-10} = rd;
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let Inst{11-15} = ra;
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let Inst{16-20} = rb;
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let Inst{21-31} = flags;
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}
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//===----------------------------------------------------------------------===//
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// Type B instruction class in MBlaze : <|opcode|rd|ra|immediate|>
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//===----------------------------------------------------------------------===//
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class TB<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin> :
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MBlazeInst<op, FRRI, outs, ins, asmstr, pattern, itin>
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{
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bits<5> rd;
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bits<5> ra;
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bits<16> imm16;
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let Inst{6-10} = rd;
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let Inst{11-15} = ra;
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let Inst{16-31} = imm16;
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}
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//===----------------------------------------------------------------------===//
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// Type A instruction class in MBlaze but with the operands reversed
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// in the LLVM DAG : <|opcode|rd|ra|rb|flags|>
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//===----------------------------------------------------------------------===//
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class TAR<bits<6> op, bits<11> flags, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin> :
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TA<op, flags, outs, ins, asmstr, pattern, itin>
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{
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bits<5> rrd;
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bits<5> rrb;
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bits<5> rra;
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let Form = FRRRR;
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let rd = rrd;
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let ra = rra;
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let rb = rrb;
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}
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//===----------------------------------------------------------------------===//
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// Type B instruction class in MBlaze but with the operands reversed in
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// the LLVM DAG : <|opcode|rd|ra|immediate|>
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//===----------------------------------------------------------------------===//
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class TBR<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin> :
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TB<op, outs, ins, asmstr, pattern, itin> {
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bits<5> rrd;
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bits<16> rimm16;
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bits<5> rra;
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let Form = FRIR;
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let rd = rrd;
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let ra = rra;
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let imm16 = rimm16;
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}
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//===----------------------------------------------------------------------===//
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// Shift immediate instruction class in MBlaze : <|opcode|rd|ra|immediate|>
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//===----------------------------------------------------------------------===//
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class SHT<bits<6> op, bits<2> flags, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<op, FRRI, outs, ins, asmstr, pattern, itin> {
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bits<5> rd;
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bits<5> ra;
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bits<5> imm5;
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let Inst{6-10} = rd;
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let Inst{11-15} = ra;
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let Inst{16-20} = 0x0;
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let Inst{21-22} = flags;
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let Inst{23-26} = 0x0;
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let Inst{27-31} = imm5;
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}
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//===----------------------------------------------------------------------===//
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// Special instruction class in MBlaze : <|opcode|rd|imm14|>
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//===----------------------------------------------------------------------===//
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class SPC<bits<6> op, bits<2> flags, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<op, FRI, outs, ins, asmstr, pattern, itin> {
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bits<5> rd;
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bits<14> imm14;
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let Inst{6-10} = rd;
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let Inst{11-15} = 0x0;
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let Inst{16-17} = flags;
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let Inst{18-31} = imm14;
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}
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//===----------------------------------------------------------------------===//
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// MSR instruction class in MBlaze : <|opcode|rd|imm15|>
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//===----------------------------------------------------------------------===//
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class MSR<bits<6> op, bits<6> flags, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<op, FRI, outs, ins, asmstr, pattern, itin> {
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bits<5> rd;
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bits<15> imm15;
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let Inst{6-10} = rd;
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let Inst{11-16} = flags;
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let Inst{17-31} = imm15;
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}
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