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code in preparation for code generation. The main thing it does is handle the case when eh.exception calls (and, in a future patch, eh.selector calls) are far away from landing pads. Right now in practice you only find eh.exception calls close to landing pads: either in a landing pad (the common case) or in a landing pad successor, due to loop passes shifting them about. However future exception handling improvements will result in calls far from landing pads: (1) Inlining of rewinds. Consider the following case: In function @f: ... invoke @g to label %normal unwind label %unwinds ... unwinds: %ex = call i8* @llvm.eh.exception() ... In function @g: ... invoke @something to label %continue unwind label %handler ... handler: %ex = call i8* @llvm.eh.exception() ... perform cleanups ... "rethrow exception" Now inline @g into @f. Currently this is turned into: In function @f: ... invoke @something to label %continue unwind label %handler ... handler: %ex = call i8* @llvm.eh.exception() ... perform cleanups ... invoke "rethrow exception" to label %normal unwind label %unwinds unwinds: %ex = call i8* @llvm.eh.exception() ... However we would like to simplify invoke of "rethrow exception" into a branch to the %unwinds label. Then %unwinds is no longer a landing pad, and the eh.exception call there is then far away from any landing pads. (2) Using the unwind instruction for cleanups. It would be nice to have codegen handle the following case: invoke @something to label %continue unwind label %run_cleanups ... handler: ... perform cleanups ... unwind This requires turning "unwind" into a library call, which necessarily takes a pointer to the exception as an argument (this patch also does this unwind lowering). But that means you are using eh.exception again far from a landing pad. (3) Bugpoint simplifications. When bugpoint is simplifying exception handling code it often generates eh.exception calls far from a landing pad, which then causes codegen to assert. Bugpoint then latches on to this assertion and loses sight of the original problem. Note that it is currently rare for this pass to actually do anything. And in fact it normally shouldn't do anything at all given the code coming out of llvm-gcc! But it does fire a few times in the testsuite. As far as I can see this is almost always due to the LoopStrengthReduce codegen pass introducing pointless loop preheader blocks which are landing pads and only contain a branch to another block. This other block contains an eh.exception call. So probably by tweaking LoopStrengthReduce a bit this can be avoided. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72276 91177308-0d34-0410-b5e6-96231b3b80d8
247 lines
8.2 KiB
C++
247 lines
8.2 KiB
C++
//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LLVMTargetMachine class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/Pass.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/Analysis/LoopPass.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/GCStrategy.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetAsmInfo.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace llvm {
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bool EnableFastISel;
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}
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static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
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cl::desc("Print LLVM IR produced by the loop-reduce pass"));
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static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
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cl::desc("Print LLVM IR input to isel pass"));
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static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
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cl::desc("Dump emitter generated instructions as assembly"));
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static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
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cl::desc("Dump garbage collector data"));
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static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
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cl::desc("Verify generated machine code"),
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cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
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// When this works it will be on by default.
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static cl::opt<bool>
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DisablePostRAScheduler("disable-post-RA-scheduler",
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cl::desc("Disable scheduling after register allocation"),
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cl::init(true));
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// Enable or disable FastISel. Both options are needed, because
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// FastISel is enabled by default with -fast, and we wish to be
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// able to enable or disable fast-isel independently from -fast.
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static cl::opt<cl::boolOrDefault>
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EnableFastISelOption("fast-isel", cl::Hidden,
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cl::desc("Enable the experimental \"fast\" instruction selector"));
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FileModel::Model
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LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
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raw_ostream &Out,
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CodeGenFileType FileType,
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CodeGenOpt::Level OptLevel) {
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// Add common CodeGen passes.
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if (addCommonCodeGenPasses(PM, OptLevel))
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return FileModel::Error;
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// Fold redundant debug labels.
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PM.add(createDebugLabelFoldingPass());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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if (OptLevel != CodeGenOpt::None)
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PM.add(createCodePlacementOptPass());
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switch (FileType) {
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default:
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break;
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case TargetMachine::AssemblyFile:
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if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
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return FileModel::Error;
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return FileModel::AsmFile;
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case TargetMachine::ObjectFile:
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if (getMachOWriterInfo())
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return FileModel::MachOFile;
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else if (getELFWriterInfo())
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return FileModel::ElfFile;
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}
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return FileModel::Error;
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}
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/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
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/// be split up (e.g., to add an object writer pass), this method can be used to
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/// finish up adding passes to emit the file, if necessary.
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bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
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MachineCodeEmitter *MCE,
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CodeGenOpt::Level OptLevel) {
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if (MCE)
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addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
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PM.add(createGCInfoDeleter());
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// Delete machine code for this function
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PM.add(createMachineCodeDeleter());
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return false; // success!
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}
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
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/// get machine code emitted. This uses a MachineCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method should returns true if machine code emission is
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/// not supported.
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///
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bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
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MachineCodeEmitter &MCE,
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CodeGenOpt::Level OptLevel) {
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// Add common CodeGen passes.
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if (addCommonCodeGenPasses(PM, OptLevel))
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return true;
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if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
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PM.add(createGCInfoDeleter());
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// Delete machine code for this function
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PM.add(createMachineCodeDeleter());
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return false; // success!
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}
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static void printAndVerify(PassManagerBase &PM,
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bool allowDoubleDefs = false) {
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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if (VerifyMachineCode)
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PM.add(createMachineVerifierPass(allowDoubleDefs));
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}
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/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
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/// emitting to assembly files or machine code output.
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///
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bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// Standard LLVM-Level Passes.
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// Run loop strength reduction before anything else.
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if (OptLevel != CodeGenOpt::None) {
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PM.add(createLoopStrengthReducePass(getTargetLowering()));
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if (PrintLSR)
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PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
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}
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// Turn exception handling constructs into something the code generators can
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// handle.
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if (!getTargetAsmInfo()->doesSupportExceptionHandling())
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PM.add(createLowerInvokePass(getTargetLowering()));
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else
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PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
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PM.add(createGCLoweringPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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if (OptLevel != CodeGenOpt::None)
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PM.add(createCodeGenPreparePass(getTargetLowering()));
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PM.add(createStackProtectorPass(getTargetLowering()));
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if (PrintISelInput)
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PM.add(createPrintFunctionPass("\n\n"
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"*** Final LLVM Code input to ISel ***\n",
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&errs()));
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// Standard Lower-Level Passes.
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// Enable FastISel with -fast, but allow that to be overridden.
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if (EnableFastISelOption == cl::BOU_TRUE ||
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(OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
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EnableFastISel = true;
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// Ask the target for an isel.
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if (addInstSelector(PM, OptLevel))
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return true;
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// Print the instruction selected machine code...
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printAndVerify(PM, /* allowDoubleDefs= */ true);
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if (OptLevel != CodeGenOpt::None) {
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PM.add(createMachineLICMPass());
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PM.add(createMachineSinkingPass());
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printAndVerify(PM, /* allowDoubleDefs= */ true);
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}
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// Run pre-ra passes.
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if (addPreRegAlloc(PM, OptLevel))
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printAndVerify(PM);
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// Perform register allocation.
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PM.add(createRegisterAllocator());
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// Perform stack slot coloring.
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if (OptLevel != CodeGenOpt::None)
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PM.add(createStackSlotColoringPass(OptLevel >= CodeGenOpt::Aggressive));
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printAndVerify(PM); // Print the register-allocated code
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// Run post-ra passes.
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if (addPostRegAlloc(PM, OptLevel))
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printAndVerify(PM);
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PM.add(createLowerSubregsPass());
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printAndVerify(PM);
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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PM.add(createPrologEpilogCodeInserter());
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printAndVerify(PM);
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// Second pass scheduler.
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if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
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PM.add(createPostRAScheduler());
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printAndVerify(PM);
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}
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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if (OptLevel != CodeGenOpt::None) {
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PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
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printAndVerify(PM);
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}
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PM.add(createGCMachineCodeAnalysisPass());
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printAndVerify(PM);
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if (PrintGCInfo)
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PM.add(createGCInfoPrinter(*cerr));
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return false;
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}
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