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https://github.com/c64scene-ar/llvm-6502.git
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b6606e46ab
Unlike most -- hopefully "all other", but I'm still checking -- memory
instructions we support, LOAD REVERSED and STORE REVERSED may access
the memory location several times. This means that they are not suitable
for volatile loads and stores.
This patch is a prerequisite for better atomic load and store support.
The same principle applies there: almost all memory instructions we
support are inherently atomic ("block concurrent"), but LOAD REVERSED
and STORE REVERSED are exceptions.
Other instructions continue to allow volatile operands. I will add
positive "allows volatile" tests at the same time as the "allows atomic
load or store" tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183002 91177308-0d34-0410-b5e6-96231b3b80d8
214 lines
11 KiB
TableGen
214 lines
11 KiB
TableGen
//===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Type profiles
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//===----------------------------------------------------------------------===//
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def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>]>;
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def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>,
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SDTCisVT<1, i64>]>;
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def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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def SDT_ZBRCCMask : SDTypeProfile<0, 2,
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[SDTCisVT<0, i8>,
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SDTCisVT<1, OtherVT>]>;
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def SDT_ZSelectCCMask : SDTypeProfile<1, 3,
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[SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>,
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SDTCisVT<3, i8>]>;
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def SDT_ZWrapPtr : SDTypeProfile<1, 1,
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[SDTCisSameAs<0, 1>,
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SDTCisPtrTy<0>]>;
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def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
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def SDT_ZExtractAccess : SDTypeProfile<1, 1,
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[SDTCisVT<0, i32>,
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SDTCisVT<1, i8>]>;
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def SDT_ZGR128Binary32 : SDTypeProfile<1, 2,
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[SDTCisVT<0, untyped>,
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SDTCisVT<1, untyped>,
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SDTCisVT<2, i32>]>;
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def SDT_ZGR128Binary64 : SDTypeProfile<1, 2,
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[SDTCisVT<0, untyped>,
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SDTCisVT<1, untyped>,
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SDTCisVT<2, i64>]>;
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def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5,
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[SDTCisVT<0, i32>,
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SDTCisPtrTy<1>,
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SDTCisVT<2, i32>,
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SDTCisVT<3, i32>,
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SDTCisVT<4, i32>,
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SDTCisVT<5, i32>]>;
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def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6,
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[SDTCisVT<0, i32>,
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SDTCisPtrTy<1>,
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SDTCisVT<2, i32>,
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SDTCisVT<3, i32>,
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SDTCisVT<4, i32>,
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SDTCisVT<5, i32>,
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SDTCisVT<6, i32>]>;
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//===----------------------------------------------------------------------===//
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// Node definitions
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//===----------------------------------------------------------------------===//
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// These are target-independent nodes, but have target-specific formats.
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
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[SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
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[SDNPHasChain, SDNPSideEffect, SDNPOptInGlue,
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SDNPOutGlue]>;
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// Nodes for SystemZISD::*. See SystemZISelLowering.h for more details.
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def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall,
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[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
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SDNPVariadic]>;
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def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>;
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def z_cmp : SDNode<"SystemZISD::CMP", SDT_ZCmp, [SDNPOutGlue]>;
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def z_ucmp : SDNode<"SystemZISD::UCMP", SDT_ZCmp, [SDNPOutGlue]>;
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def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask,
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[SDNPHasChain, SDNPInGlue]>;
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def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask,
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[SDNPInGlue]>;
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def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>;
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def z_extract_access : SDNode<"SystemZISD::EXTRACT_ACCESS",
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SDT_ZExtractAccess>;
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def z_umul_lohi64 : SDNode<"SystemZISD::UMUL_LOHI64", SDT_ZGR128Binary64>;
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def z_sdivrem64 : SDNode<"SystemZISD::SDIVREM64", SDT_ZGR128Binary64>;
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def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>;
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def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>;
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class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW>
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: SDNode<"SystemZISD::"##name, profile,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
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def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">;
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def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">;
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def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">;
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def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">;
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def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">;
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def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">;
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def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">;
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def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">;
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def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">;
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def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">;
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def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">;
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def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>;
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//===----------------------------------------------------------------------===//
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// Pattern fragments
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//===----------------------------------------------------------------------===//
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// Register sign-extend operations. Sub-32-bit values are represented as i32s.
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def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>;
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def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>;
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def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>;
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// Register zero-extend operations. Sub-32-bit values are represented as i32s.
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def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>;
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def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>;
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def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>;
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// Typed floating-point loads.
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def loadf32 : PatFrag<(ops node:$src), (f32 (load node:$src))>;
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def loadf64 : PatFrag<(ops node:$src), (f64 (load node:$src))>;
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// Aligned loads.
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class AlignedLoad<SDPatternOperator load>
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: PatFrag<(ops node:$addr), (load node:$addr), [{
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LoadSDNode *Load = cast<LoadSDNode>(N);
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return Load->getAlignment() >= Load->getMemoryVT().getStoreSize();
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}]>;
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def aligned_load : AlignedLoad<load>;
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def aligned_sextloadi16 : AlignedLoad<sextloadi16>;
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def aligned_sextloadi32 : AlignedLoad<sextloadi32>;
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def aligned_zextloadi16 : AlignedLoad<zextloadi16>;
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def aligned_zextloadi32 : AlignedLoad<zextloadi32>;
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// Aligned stores.
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class AlignedStore<SDPatternOperator store>
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: PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
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StoreSDNode *Store = cast<StoreSDNode>(N);
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return Store->getAlignment() >= Store->getMemoryVT().getStoreSize();
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}]>;
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def aligned_store : AlignedStore<store>;
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def aligned_truncstorei16 : AlignedStore<truncstorei16>;
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def aligned_truncstorei32 : AlignedStore<truncstorei32>;
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// Non-volatile loads. Used for instructions that might access the storage
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// location multiple times.
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class NonvolatileLoad<SDPatternOperator load>
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: PatFrag<(ops node:$addr), (load node:$addr), [{
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LoadSDNode *Load = cast<LoadSDNode>(N);
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return !Load->isVolatile();
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}]>;
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def nonvolatile_load : NonvolatileLoad<load>;
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// Non-volatile stores.
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class NonvolatileStore<SDPatternOperator store>
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: PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
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StoreSDNode *Store = cast<StoreSDNode>(N);
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return !Store->isVolatile();
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}]>;
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def nonvolatile_store : NonvolatileStore<store>;
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// Insertions.
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def inserti8 : PatFrag<(ops node:$src1, node:$src2),
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(or (and node:$src1, -256), node:$src2)>;
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def insertll : PatFrag<(ops node:$src1, node:$src2),
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(or (and node:$src1, 0xffffffffffff0000), node:$src2)>;
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def insertlh : PatFrag<(ops node:$src1, node:$src2),
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(or (and node:$src1, 0xffffffff0000ffff), node:$src2)>;
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def inserthl : PatFrag<(ops node:$src1, node:$src2),
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(or (and node:$src1, 0xffff0000ffffffff), node:$src2)>;
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def inserthh : PatFrag<(ops node:$src1, node:$src2),
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(or (and node:$src1, 0x0000ffffffffffff), node:$src2)>;
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def insertlf : PatFrag<(ops node:$src1, node:$src2),
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(or (and node:$src1, 0xffffffff00000000), node:$src2)>;
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def inserthf : PatFrag<(ops node:$src1, node:$src2),
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(or (and node:$src1, 0x00000000ffffffff), node:$src2)>;
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// ORs that can be treated as insertions.
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def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2),
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(or node:$src1, node:$src2), [{
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unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
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return CurDAG->MaskedValueIsZero(N->getOperand(0),
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APInt::getLowBitsSet(BitWidth, 8));
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}]>;
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// ORs that can be treated as reversed insertions.
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def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2),
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(or node:$src1, node:$src2), [{
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unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
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return CurDAG->MaskedValueIsZero(N->getOperand(1),
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APInt::getLowBitsSet(BitWidth, 8));
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}]>;
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// Fused multiply-add and multiply-subtract, but with the order of the
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// operands matching SystemZ's MA and MS instructions.
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def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
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(fma node:$src2, node:$src3, node:$src1)>;
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def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
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(fma node:$src2, node:$src3, (fneg node:$src1))>;
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// Floating-point negative absolute.
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def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>;
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// Create a unary operator that loads from memory and then performs
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// the given operation on it.
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class loadu<SDPatternOperator operator, SDPatternOperator load = load>
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: PatFrag<(ops node:$addr), (operator (load node:$addr))>;
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// Create a store operator that performs the given unary operation
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// on the value before storing it.
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class storeu<SDPatternOperator operator, SDPatternOperator store = store>
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: PatFrag<(ops node:$value, node:$addr),
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(store (operator node:$value), node:$addr)>;
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