Tom Stellard ad7ecc65b1 R600: Make sure to schedule AR register uses and defs in the same clause ... Reviewed-by: vljn at ovi.com git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183294 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-05 03:43:06 +00:00
..
AArch64
ARM	Cortex-R5 can issue Thumb2 integer division instructions.	2013-06-04 22:52:09 +00:00
CPP
Generic
Hexagon
Inputs
MBlaze
Mips	[mips] Big-endian code generation for atomic instructions.	2013-05-31 03:25:44 +00:00
MSP430
NVPTX	[NVPTX] Re-enable support for virtual registers in the final output	2013-05-31 12:14:49 +00:00
PowerPC
R600	R600: Make sure to schedule AR register uses and defs in the same clause	2013-06-05 03:43:06 +00:00
SI
SPARC	Sparc: Add support for indirect branch and blockaddress in Sparc backend.	2013-06-03 05:58:33 +00:00
SystemZ	[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses	2013-05-31 13:25:22 +00:00
Thumb
Thumb2	Cortex-R5 can issue Thumb2 integer division instructions.	2013-06-04 22:52:09 +00:00
X86	Revert r183069: "TMP: LEA64_32r fixing"	2013-06-01 10:23:46 +00:00
XCore