mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2397 91177308-0d34-0410-b5e6-96231b3b80d8
1034 lines
35 KiB
C++
1034 lines
35 KiB
C++
// $Id$
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//***************************************************************************
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// File:
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// SchedGraph.cpp
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//
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// Purpose:
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// Scheduling graph based on SSA graph plus extra dependence edges
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// capturing dependences due to machine resources (machine registers,
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// CC registers, and any others).
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//
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// History:
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// 7/20/01 - Vikram Adve - Created
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//**************************************************************************/
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#include "SchedGraph.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/Target/MachineRegInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/BasicBlock.h"
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#include "llvm/Function.h"
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#include "llvm/iOther.h"
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#include "Support/StringExtras.h"
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#include "Support/STLExtras.h"
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#include <iostream>
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using std::vector;
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using std::pair;
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using std::hash_map;
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using std::cerr;
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//*********************** Internal Data Structures *************************/
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// The following two types need to be classes, not typedefs, so we can use
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// opaque declarations in SchedGraph.h
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//
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struct RefVec: public vector< pair<SchedGraphNode*, int> > {
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typedef vector< pair<SchedGraphNode*, int> >:: iterator iterator;
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typedef vector< pair<SchedGraphNode*, int> >::const_iterator const_iterator;
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};
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struct RegToRefVecMap: public hash_map<int, RefVec> {
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typedef hash_map<int, RefVec>:: iterator iterator;
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typedef hash_map<int, RefVec>::const_iterator const_iterator;
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};
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struct ValueToDefVecMap: public hash_map<const Instruction*, RefVec> {
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typedef hash_map<const Instruction*, RefVec>:: iterator iterator;
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typedef hash_map<const Instruction*, RefVec>::const_iterator const_iterator;
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};
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//
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// class SchedGraphEdge
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//
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/*ctor*/
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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SchedGraphEdgeDepType _depType,
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unsigned int _depOrderType,
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(_depType),
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depOrderType(_depOrderType),
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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val(NULL)
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{
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assert(src != sink && "Self-loop in scheduling graph!");
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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/*ctor*/
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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const Value* _val,
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unsigned int _depOrderType,
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(ValueDep),
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depOrderType(_depOrderType),
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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val(_val)
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{
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assert(src != sink && "Self-loop in scheduling graph!");
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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/*ctor*/
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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unsigned int _regNum,
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unsigned int _depOrderType,
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(MachineRegister),
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depOrderType(_depOrderType),
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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machineRegNum(_regNum)
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{
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assert(src != sink && "Self-loop in scheduling graph!");
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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/*ctor*/
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SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
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SchedGraphNode* _sink,
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ResourceId _resourceId,
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int _minDelay)
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: src(_src),
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sink(_sink),
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depType(MachineResource),
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depOrderType(NonDataDep),
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minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
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resourceId(_resourceId)
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{
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assert(src != sink && "Self-loop in scheduling graph!");
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src->addOutEdge(this);
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sink->addInEdge(this);
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}
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/*dtor*/
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SchedGraphEdge::~SchedGraphEdge()
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{
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}
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void SchedGraphEdge::dump(int indent=0) const {
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cerr << std::string(indent*2, ' ') << *this;
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}
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//
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// class SchedGraphNode
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//
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/*ctor*/
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SchedGraphNode::SchedGraphNode(unsigned int _nodeId,
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const BasicBlock* _bb,
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const MachineInstr* _minstr,
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int indexInBB,
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const TargetMachine& target)
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: nodeId(_nodeId),
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bb(_bb),
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minstr(_minstr),
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origIndexInBB(indexInBB),
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latency(0)
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{
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if (minstr)
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{
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MachineOpCode mopCode = minstr->getOpCode();
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latency = target.getInstrInfo().hasResultInterlock(mopCode)
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? target.getInstrInfo().minLatency(mopCode)
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: target.getInstrInfo().maxLatency(mopCode);
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}
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}
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/*dtor*/
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SchedGraphNode::~SchedGraphNode()
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{
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// for each node, delete its out-edges
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std::for_each(beginOutEdges(), endOutEdges(),
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deleter<SchedGraphEdge>);
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}
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void SchedGraphNode::dump(int indent=0) const {
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cerr << std::string(indent*2, ' ') << *this;
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}
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inline void
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SchedGraphNode::addInEdge(SchedGraphEdge* edge)
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{
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inEdges.push_back(edge);
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}
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inline void
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SchedGraphNode::addOutEdge(SchedGraphEdge* edge)
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{
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outEdges.push_back(edge);
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}
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inline void
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SchedGraphNode::removeInEdge(const SchedGraphEdge* edge)
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{
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assert(edge->getSink() == this);
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for (iterator I = beginInEdges(); I != endInEdges(); ++I)
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if ((*I) == edge)
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{
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inEdges.erase(I);
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break;
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}
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}
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inline void
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SchedGraphNode::removeOutEdge(const SchedGraphEdge* edge)
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{
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assert(edge->getSrc() == this);
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for (iterator I = beginOutEdges(); I != endOutEdges(); ++I)
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if ((*I) == edge)
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{
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outEdges.erase(I);
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break;
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}
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}
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//
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// class SchedGraph
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//
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/*ctor*/
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SchedGraph::SchedGraph(const BasicBlock* bb,
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const TargetMachine& target)
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{
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bbVec.push_back(bb);
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buildGraph(target);
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}
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/*dtor*/
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SchedGraph::~SchedGraph()
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{
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for (const_iterator I = begin(); I != end(); ++I)
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delete I->second;
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delete graphRoot;
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delete graphLeaf;
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}
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void
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SchedGraph::dump() const
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{
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cerr << " Sched Graph for Basic Blocks: ";
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for (unsigned i=0, N=bbVec.size(); i < N; i++)
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{
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cerr << (bbVec[i]->hasName()? bbVec[i]->getName() : "block")
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<< " (" << bbVec[i] << ")"
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<< ((i == N-1)? "" : ", ");
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}
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cerr << "\n\n Actual Root nodes : ";
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for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
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cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
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<< ((i == N-1)? "" : ", ");
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cerr << "\n Graph Nodes:\n";
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for (const_iterator I=begin(); I != end(); ++I)
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cerr << "\n" << *I->second;
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cerr << "\n";
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}
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void
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SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
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{
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// Delete and disconnect all in-edges for the node
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for (SchedGraphNode::iterator I = node->beginInEdges();
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I != node->endInEdges(); ++I)
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{
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SchedGraphNode* srcNode = (*I)->getSrc();
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srcNode->removeOutEdge(*I);
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delete *I;
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if (addDummyEdges &&
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srcNode != getRoot() &&
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srcNode->beginOutEdges() == srcNode->endOutEdges())
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{ // srcNode has no more out edges, so add an edge to dummy EXIT node
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assert(node != getLeaf() && "Adding edge that was just removed?");
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(void) new SchedGraphEdge(srcNode, getLeaf(),
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SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
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}
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}
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node->inEdges.clear();
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}
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void
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SchedGraph::eraseOutgoingEdges(SchedGraphNode* node, bool addDummyEdges)
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{
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// Delete and disconnect all out-edges for the node
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for (SchedGraphNode::iterator I = node->beginOutEdges();
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I != node->endOutEdges(); ++I)
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{
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SchedGraphNode* sinkNode = (*I)->getSink();
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sinkNode->removeInEdge(*I);
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delete *I;
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if (addDummyEdges &&
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sinkNode != getLeaf() &&
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sinkNode->beginInEdges() == sinkNode->endInEdges())
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{ //sinkNode has no more in edges, so add an edge from dummy ENTRY node
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assert(node != getRoot() && "Adding edge that was just removed?");
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(void) new SchedGraphEdge(getRoot(), sinkNode,
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SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
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}
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}
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node->outEdges.clear();
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}
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void
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SchedGraph::eraseIncidentEdges(SchedGraphNode* node, bool addDummyEdges)
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{
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this->eraseIncomingEdges(node, addDummyEdges);
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this->eraseOutgoingEdges(node, addDummyEdges);
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}
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void
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SchedGraph::addDummyEdges()
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{
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assert(graphRoot->outEdges.size() == 0);
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for (const_iterator I=begin(); I != end(); ++I)
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{
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SchedGraphNode* node = (*I).second;
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assert(node != graphRoot && node != graphLeaf);
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if (node->beginInEdges() == node->endInEdges())
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(void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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if (node->beginOutEdges() == node->endOutEdges())
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(void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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}
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void
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SchedGraph::addCDEdges(const TerminatorInst* term,
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const TargetMachine& target)
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{
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const MachineInstrInfo& mii = target.getInstrInfo();
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MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
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// Find the first branch instr in the sequence of machine instrs for term
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//
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unsigned first = 0;
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while (!mii.isBranch(termMvec[first]->getOpCode()))
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++first;
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assert(first < termMvec.size() &&
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"No branch instructions for BR? Ok, but weird! Delete assertion.");
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if (first == termMvec.size())
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return;
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SchedGraphNode* firstBrNode = this->getGraphNodeForInstr(termMvec[first]);
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// Add CD edges from each instruction in the sequence to the
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// *last preceding* branch instr. in the sequence
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// Use a latency of 0 because we only need to prevent out-of-order issue.
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//
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for (int i = (int) termMvec.size()-1; i > (int) first; i--)
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{
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SchedGraphNode* toNode = this->getGraphNodeForInstr(termMvec[i]);
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assert(toNode && "No node for instr generated for branch?");
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for (int j = i-1; j >= 0; j--)
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if (mii.isBranch(termMvec[j]->getOpCode()))
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{
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SchedGraphNode* brNode = this->getGraphNodeForInstr(termMvec[j]);
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assert(brNode && "No node for instr generated for branch?");
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(void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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break; // only one incoming edge is enough
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}
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}
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// Add CD edges from each instruction preceding the first branch
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// to the first branch. Use a latency of 0 as above.
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//
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for (int i = first-1; i >= 0; i--)
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{
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SchedGraphNode* fromNode = this->getGraphNodeForInstr(termMvec[i]);
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assert(fromNode && "No node for instr generated for branch?");
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(void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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// Now add CD edges to the first branch instruction in the sequence from
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// all preceding instructions in the basic block. Use 0 latency again.
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//
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const BasicBlock* bb = firstBrNode->getBB();
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const MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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{
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if (mvec[i] == termMvec[first]) // reached the first branch
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break;
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SchedGraphNode* fromNode = this->getGraphNodeForInstr(mvec[i]);
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if (fromNode == NULL)
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continue; // dummy instruction, e.g., PHI
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(void) new SchedGraphEdge(fromNode, firstBrNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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// If we find any other machine instructions (other than due to
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// the terminator) that also have delay slots, add an outgoing edge
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// from the instruction to the instructions in the delay slots.
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//
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unsigned d = mii.getNumDelaySlots(mvec[i]->getOpCode());
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assert(i+d < N && "Insufficient delay slots for instruction?");
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for (unsigned j=1; j <= d; j++)
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{
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SchedGraphNode* toNode = this->getGraphNodeForInstr(mvec[i+j]);
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assert(toNode && "No node for machine instr in delay slot?");
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(void) new SchedGraphEdge(fromNode, toNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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}
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}
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static const int SG_LOAD_REF = 0;
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static const int SG_STORE_REF = 1;
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static const int SG_CALL_REF = 2;
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static const unsigned int SG_DepOrderArray[][3] = {
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{ SchedGraphEdge::NonDataDep,
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SchedGraphEdge::AntiDep,
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SchedGraphEdge::AntiDep },
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{ SchedGraphEdge::TrueDep,
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SchedGraphEdge::OutputDep,
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SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
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{ SchedGraphEdge::TrueDep,
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SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
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SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
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| SchedGraphEdge::OutputDep }
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};
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// Add a dependence edge between every pair of machine load/store/call
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// instructions, where at least one is a store or a call.
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// Use latency 1 just to ensure that memory operations are ordered;
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// latency does not otherwise matter (true dependences enforce that).
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//
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void
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SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
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const TargetMachine& target)
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{
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const MachineInstrInfo& mii = target.getInstrInfo();
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// Instructions in memNodeVec are in execution order within the basic block,
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// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
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//
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for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
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{
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MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
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int fromType = mii.isCall(fromOpCode)? SG_CALL_REF
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: mii.isLoad(fromOpCode)? SG_LOAD_REF
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: SG_STORE_REF;
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for (unsigned jm=im+1; jm < NM; jm++)
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{
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MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
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int toType = mii.isCall(toOpCode)? SG_CALL_REF
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: mii.isLoad(toOpCode)? SG_LOAD_REF
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: SG_STORE_REF;
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if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
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(void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
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SchedGraphEdge::MemoryDep,
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SG_DepOrderArray[fromType][toType], 1);
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}
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}
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}
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// Add edges from/to CC reg instrs to/from call instrs.
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// Essentially this prevents anything that sets or uses a CC reg from being
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// reordered w.r.t. a call.
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// Use a latency of 0 because we only need to prevent out-of-order issue,
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// like with control dependences.
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//
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void
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SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
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MachineCodeForBasicBlock& bbMvec,
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const TargetMachine& target)
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{
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const MachineInstrInfo& mii = target.getInstrInfo();
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vector<SchedGraphNode*> callNodeVec;
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// Find the call instruction nodes and put them in a vector.
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for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
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if (mii.isCall(memNodeVec[im]->getOpCode()))
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callNodeVec.push_back(memNodeVec[im]);
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// Now walk the entire basic block, looking for CC instructions *and*
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// call instructions, and keep track of the order of the instructions.
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// Use the call node vec to quickly find earlier and later call nodes
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// relative to the current CC instruction.
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//
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int lastCallNodeIdx = -1;
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for (unsigned i=0, N=bbMvec.size(); i < N; i++)
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if (mii.isCall(bbMvec[i]->getOpCode()))
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{
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++lastCallNodeIdx;
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for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
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if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
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break;
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assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
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}
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else if (mii.isCCInstr(bbMvec[i]->getOpCode()))
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{ // Add incoming/outgoing edges from/to preceding/later calls
|
|
SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
|
|
int j=0;
|
|
for ( ; j <= lastCallNodeIdx; j++)
|
|
(void) new SchedGraphEdge(callNodeVec[j], ccNode,
|
|
MachineCCRegsRID, 0);
|
|
for ( ; j < (int) callNodeVec.size(); j++)
|
|
(void) new SchedGraphEdge(ccNode, callNodeVec[j],
|
|
MachineCCRegsRID, 0);
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
|
|
const TargetMachine& target)
|
|
{
|
|
assert(bbVec.size() == 1 && "Only handling a single basic block here");
|
|
|
|
// This assumes that such hardwired registers are never allocated
|
|
// to any LLVM value (since register allocation happens later), i.e.,
|
|
// any uses or defs of this register have been made explicit!
|
|
// Also assumes that two registers with different numbers are
|
|
// not aliased!
|
|
//
|
|
for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
|
|
I != regToRefVecMap.end(); ++I)
|
|
{
|
|
int regNum = (*I).first;
|
|
RefVec& regRefVec = (*I).second;
|
|
|
|
// regRefVec is ordered by control flow order in the basic block
|
|
for (unsigned i=0; i < regRefVec.size(); ++i)
|
|
{
|
|
SchedGraphNode* node = regRefVec[i].first;
|
|
unsigned int opNum = regRefVec[i].second;
|
|
bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
|
|
|
|
for (unsigned p=0; p < i; ++p)
|
|
{
|
|
SchedGraphNode* prevNode = regRefVec[p].first;
|
|
if (prevNode != node)
|
|
{
|
|
unsigned int prevOpNum = regRefVec[p].second;
|
|
bool prevIsDef =
|
|
prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
|
|
|
|
if (isDef)
|
|
new SchedGraphEdge(prevNode, node, regNum,
|
|
(prevIsDef)? SchedGraphEdge::OutputDep
|
|
: SchedGraphEdge::AntiDep);
|
|
else if (prevIsDef)
|
|
new SchedGraphEdge(prevNode, node, regNum,
|
|
SchedGraphEdge::TrueDep);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
|
|
const RefVec& defVec,
|
|
const Value* defValue,
|
|
bool refNodeIsDef,
|
|
const TargetMachine& target)
|
|
{
|
|
// Add true or output dep edges from all def nodes before refNode in BB.
|
|
// Add anti or output dep edges to all def nodes after refNode.
|
|
for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
|
|
{
|
|
if ((*I).first == refNode)
|
|
continue; // Dont add any self-loops
|
|
|
|
if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB())
|
|
// (*).first is before refNode
|
|
(void) new SchedGraphEdge((*I).first, refNode, defValue,
|
|
(refNodeIsDef)? SchedGraphEdge::OutputDep
|
|
: SchedGraphEdge::TrueDep);
|
|
else
|
|
// (*).first is after refNode
|
|
(void) new SchedGraphEdge(refNode, (*I).first, defValue,
|
|
(refNodeIsDef)? SchedGraphEdge::OutputDep
|
|
: SchedGraphEdge::AntiDep);
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
|
|
const ValueToDefVecMap& valueToDefVecMap,
|
|
const TargetMachine& target)
|
|
{
|
|
SchedGraphNode* node = this->getGraphNodeForInstr(&minstr);
|
|
if (node == NULL)
|
|
return;
|
|
|
|
// Add edges for all operands of the machine instruction.
|
|
//
|
|
for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
|
|
{
|
|
const MachineOperand& mop = minstr.getOperand(i);
|
|
switch(mop.getOperandType())
|
|
{
|
|
case MachineOperand::MO_VirtualRegister:
|
|
case MachineOperand::MO_CCRegister:
|
|
if (const Instruction* srcI =
|
|
dyn_cast_or_null<Instruction>(mop.getVRegValue()))
|
|
{
|
|
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
|
|
if (I != valueToDefVecMap.end())
|
|
addEdgesForValue(node, (*I).second, mop.getVRegValue(),
|
|
minstr.operandIsDefined(i), target);
|
|
}
|
|
break;
|
|
|
|
case MachineOperand::MO_MachineRegister:
|
|
break;
|
|
|
|
case MachineOperand::MO_SignExtendedImmed:
|
|
case MachineOperand::MO_UnextendedImmed:
|
|
case MachineOperand::MO_PCRelativeDisp:
|
|
break; // nothing to do for immediate fields
|
|
|
|
default:
|
|
assert(0 && "Unknown machine operand type in SchedGraph builder");
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Add edges for values implicitly used by the machine instruction.
|
|
// Examples include function arguments to a Call instructions or the return
|
|
// value of a Ret instruction.
|
|
//
|
|
for (unsigned i=0, N=minstr.getNumImplicitRefs(); i < N; ++i)
|
|
if (! minstr.implicitRefIsDefined(i))
|
|
if (const Instruction* srcI =
|
|
dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
|
|
{
|
|
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
|
|
if (I != valueToDefVecMap.end())
|
|
addEdgesForValue(node, (*I).second, minstr.getImplicitRef(i),
|
|
minstr.implicitRefIsDefined(i), target);
|
|
}
|
|
}
|
|
|
|
|
|
#undef NEED_SEPARATE_NONSSA_EDGES_CODE
|
|
#ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
|
|
void
|
|
SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
|
|
const TargetMachine& target)
|
|
{
|
|
if (isa<PHINode>(instr))
|
|
return;
|
|
|
|
MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
|
|
const MachineInstrInfo& mii = target.getInstrInfo();
|
|
RefVec refVec;
|
|
|
|
for (unsigned i=0, N=mvec.size(); i < N; i++)
|
|
for (int o=0, N = mii.getNumOperands(mvec[i]->getOpCode()); o < N; o++)
|
|
{
|
|
const MachineOperand& mop = mvec[i]->getOperand(o);
|
|
|
|
if ((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
|
mop.getOperandType() == MachineOperand::MO_CCRegister)
|
|
&& mop.getVRegValue() == (Value*) instr)
|
|
{
|
|
// this operand is a definition or use of value `instr'
|
|
SchedGraphNode* node = this->getGraphNodeForInstr(mvec[i]);
|
|
assert(node && "No node for machine instruction in this BB?");
|
|
refVec.push_back(std::make_pair(node, o));
|
|
}
|
|
}
|
|
|
|
// refVec is ordered by control flow order of the machine instructions
|
|
for (unsigned i=0; i < refVec.size(); ++i)
|
|
{
|
|
SchedGraphNode* node = refVec[i].first;
|
|
unsigned int opNum = refVec[i].second;
|
|
bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
|
|
|
|
if (isDef)
|
|
// add output and/or anti deps to this definition
|
|
for (unsigned p=0; p < i; ++p)
|
|
{
|
|
SchedGraphNode* prevNode = refVec[p].first;
|
|
if (prevNode != node)
|
|
{
|
|
bool prevIsDef = prevNode->getMachineInstr()->
|
|
operandIsDefined(refVec[p].second);
|
|
new SchedGraphEdge(prevNode, node, SchedGraphEdge::ValueDep,
|
|
(prevIsDef)? SchedGraphEdge::OutputDep
|
|
: SchedGraphEdge::AntiDep);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif //NEED_SEPARATE_NONSSA_EDGES_CODE
|
|
|
|
|
|
void
|
|
SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
|
|
SchedGraphNode* node,
|
|
vector<SchedGraphNode*>& memNodeVec,
|
|
RegToRefVecMap& regToRefVecMap,
|
|
ValueToDefVecMap& valueToDefVecMap)
|
|
{
|
|
const MachineInstrInfo& mii = target.getInstrInfo();
|
|
|
|
|
|
MachineOpCode opCode = node->getOpCode();
|
|
if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
|
|
memNodeVec.push_back(node);
|
|
|
|
// Collect the register references and value defs. for explicit operands
|
|
//
|
|
const MachineInstr& minstr = * node->getMachineInstr();
|
|
for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
|
|
{
|
|
const MachineOperand& mop = minstr.getOperand(i);
|
|
|
|
// if this references a register other than the hardwired
|
|
// "zero" register, record the reference.
|
|
if (mop.getOperandType() == MachineOperand::MO_MachineRegister)
|
|
{
|
|
int regNum = mop.getMachineRegNum();
|
|
if (regNum != target.getRegInfo().getZeroRegNum())
|
|
regToRefVecMap[mop.getMachineRegNum()].push_back(
|
|
std::make_pair(node, i));
|
|
continue; // nothing more to do
|
|
}
|
|
|
|
// ignore all other non-def operands
|
|
if (! minstr.operandIsDefined(i))
|
|
continue;
|
|
|
|
// We must be defining a value.
|
|
assert((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
|
mop.getOperandType() == MachineOperand::MO_CCRegister)
|
|
&& "Do not expect any other kind of operand to be defined!");
|
|
|
|
const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
|
|
valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
|
|
}
|
|
|
|
//
|
|
// Collect value defs. for implicit operands. The interface to extract
|
|
// them assumes they must be virtual registers!
|
|
//
|
|
for (int i=0, N = (int) minstr.getNumImplicitRefs(); i < N; ++i)
|
|
if (minstr.implicitRefIsDefined(i))
|
|
if (const Instruction* defInstr =
|
|
dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
|
|
{
|
|
valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i));
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraph::buildNodesforBB(const TargetMachine& target,
|
|
const BasicBlock* bb,
|
|
vector<SchedGraphNode*>& memNodeVec,
|
|
RegToRefVecMap& regToRefVecMap,
|
|
ValueToDefVecMap& valueToDefVecMap)
|
|
{
|
|
const MachineInstrInfo& mii = target.getInstrInfo();
|
|
|
|
// Build graph nodes for each VM instruction and gather def/use info.
|
|
// Do both those together in a single pass over all machine instructions.
|
|
const MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
|
|
for (unsigned i=0; i < mvec.size(); i++)
|
|
if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
|
|
{
|
|
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), bb,
|
|
mvec[i], i, target);
|
|
this->noteGraphNodeForInstr(mvec[i], node);
|
|
|
|
// Remember all register references and value defs
|
|
findDefUseInfoAtInstr(target, node,
|
|
memNodeVec, regToRefVecMap,valueToDefVecMap);
|
|
}
|
|
|
|
#undef REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
|
|
#ifdef REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
|
|
// This is a BIG UGLY HACK. IT NEEDS TO BE ELIMINATED.
|
|
// Look for copy instructions inserted in this BB due to Phi instructions
|
|
// in the successor BBs.
|
|
// There MUST be exactly one copy per Phi in successor nodes.
|
|
//
|
|
for (BasicBlock::succ_const_iterator SI=bb->succ_begin(), SE=bb->succ_end();
|
|
SI != SE; ++SI)
|
|
for (BasicBlock::const_iterator PI=(*SI)->begin(), PE=(*SI)->end();
|
|
PI != PE; ++PI)
|
|
{
|
|
if ((*PI)->getOpcode() != Instruction::PHINode)
|
|
break; // No more Phis in this successor
|
|
|
|
// Find the incoming value from block bb to block (*SI)
|
|
int bbIndex = cast<PHINode>(*PI)->getBasicBlockIndex(bb);
|
|
assert(bbIndex >= 0 && "But I know bb is a predecessor of (*SI)?");
|
|
Value* inVal = cast<PHINode>(*PI)->getIncomingValue(bbIndex);
|
|
assert(inVal != NULL && "There must be an in-value on every edge");
|
|
|
|
// Find the machine instruction that makes a copy of inval to (*PI).
|
|
// This must be in the current basic block (bb).
|
|
const MachineCodeForVMInstr& mvec = (*PI)->getMachineInstrVec();
|
|
const MachineInstr* theCopy = NULL;
|
|
for (unsigned i=0; i < mvec.size() && theCopy == NULL; i++)
|
|
if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
|
|
// not a Phi: assume this is a copy and examine its operands
|
|
for (int o=0, N=(int) mvec[i]->getNumOperands(); o < N; o++)
|
|
{
|
|
const MachineOperand& mop = mvec[i]->getOperand(o);
|
|
if (mvec[i]->operandIsDefined(o))
|
|
assert(mop.getVRegValue() == (*PI) && "dest shd be my Phi");
|
|
else if (mop.getVRegValue() == inVal)
|
|
{ // found the copy!
|
|
theCopy = mvec[i];
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Found the dang instruction. Now create a node and do the rest...
|
|
if (theCopy != NULL)
|
|
{
|
|
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), bb,
|
|
theCopy, origIndexInBB++, target);
|
|
this->noteGraphNodeForInstr(theCopy, node);
|
|
findDefUseInfoAtInstr(target, node,
|
|
memNodeVec, regToRefVecMap,valueToDefVecMap);
|
|
}
|
|
}
|
|
#endif //REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraph::buildGraph(const TargetMachine& target)
|
|
{
|
|
const BasicBlock* bb = bbVec[0];
|
|
|
|
assert(bbVec.size() == 1 && "Only handling a single basic block here");
|
|
|
|
// Use this data structure to note all machine operands that compute
|
|
// ordinary LLVM values. These must be computed defs (i.e., instructions).
|
|
// Note that there may be multiple machine instructions that define
|
|
// each Value.
|
|
ValueToDefVecMap valueToDefVecMap;
|
|
|
|
// Use this data structure to note all memory instructions.
|
|
// We use this to add memory dependence edges without a second full walk.
|
|
//
|
|
// vector<const Instruction*> memVec;
|
|
vector<SchedGraphNode*> memNodeVec;
|
|
|
|
// Use this data structure to note any uses or definitions of
|
|
// machine registers so we can add edges for those later without
|
|
// extra passes over the nodes.
|
|
// The vector holds an ordered list of references to the machine reg,
|
|
// ordered according to control-flow order. This only works for a
|
|
// single basic block, hence the assertion. Each reference is identified
|
|
// by the pair: <node, operand-number>.
|
|
//
|
|
RegToRefVecMap regToRefVecMap;
|
|
|
|
// Make a dummy root node. We'll add edges to the real roots later.
|
|
graphRoot = new SchedGraphNode(0, NULL, NULL, -1, target);
|
|
graphLeaf = new SchedGraphNode(1, NULL, NULL, -1, target);
|
|
|
|
//----------------------------------------------------------------
|
|
// First add nodes for all the machine instructions in the basic block
|
|
// because this greatly simplifies identifying which edges to add.
|
|
// Do this one VM instruction at a time since the SchedGraphNode needs that.
|
|
// Also, remember the load/store instructions to add memory deps later.
|
|
//----------------------------------------------------------------
|
|
|
|
buildNodesforBB(target, bb, memNodeVec, regToRefVecMap, valueToDefVecMap);
|
|
|
|
//----------------------------------------------------------------
|
|
// Now add edges for the following (all are incoming edges except (4)):
|
|
// (1) operands of the machine instruction, including hidden operands
|
|
// (2) machine register dependences
|
|
// (3) memory load/store dependences
|
|
// (3) other resource dependences for the machine instruction, if any
|
|
// (4) output dependences when multiple machine instructions define the
|
|
// same value; all must have been generated from a single VM instrn
|
|
// (5) control dependences to branch instructions generated for the
|
|
// terminator instruction of the BB. Because of delay slots and
|
|
// 2-way conditional branches, multiple CD edges are needed
|
|
// (see addCDEdges for details).
|
|
// Also, note any uses or defs of machine registers.
|
|
//
|
|
//----------------------------------------------------------------
|
|
|
|
MachineCodeForBasicBlock& bbMvec = bb->getMachineInstrVec();
|
|
|
|
// First, add edges to the terminator instruction of the basic block.
|
|
this->addCDEdges(bb->getTerminator(), target);
|
|
|
|
// Then add memory dep edges: store->load, load->store, and store->store.
|
|
// Call instructions are treated as both load and store.
|
|
this->addMemEdges(memNodeVec, target);
|
|
|
|
// Then add edges between call instructions and CC set/use instructions
|
|
this->addCallCCEdges(memNodeVec, bbMvec, target);
|
|
|
|
// Then add incoming def-use (SSA) edges for each machine instruction.
|
|
for (unsigned i=0, N=bbMvec.size(); i < N; i++)
|
|
addEdgesForInstruction(*bbMvec[i], valueToDefVecMap, target);
|
|
|
|
#ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
|
|
// Then add non-SSA edges for all VM instructions in the block.
|
|
// We assume that all machine instructions that define a value are
|
|
// generated from the VM instruction corresponding to that value.
|
|
// TODO: This could probably be done much more efficiently.
|
|
for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
|
|
this->addNonSSAEdgesForValue(*II, target);
|
|
#endif //NEED_SEPARATE_NONSSA_EDGES_CODE
|
|
|
|
// Then add edges for dependences on machine registers
|
|
this->addMachineRegEdges(regToRefVecMap, target);
|
|
|
|
// Finally, add edges from the dummy root and to dummy leaf
|
|
this->addDummyEdges();
|
|
}
|
|
|
|
|
|
//
|
|
// class SchedGraphSet
|
|
//
|
|
|
|
/*ctor*/
|
|
SchedGraphSet::SchedGraphSet(const Function* _function,
|
|
const TargetMachine& target) :
|
|
method(_function)
|
|
{
|
|
buildGraphsForMethod(method, target);
|
|
}
|
|
|
|
|
|
/*dtor*/
|
|
SchedGraphSet::~SchedGraphSet()
|
|
{
|
|
// delete all the graphs
|
|
for(iterator I = begin(), E = end(); I != E; ++I)
|
|
delete *I; // destructor is a friend
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraphSet::dump() const
|
|
{
|
|
cerr << "======== Sched graphs for function `" << method->getName()
|
|
<< "' ========\n\n";
|
|
|
|
for (const_iterator I=begin(); I != end(); ++I)
|
|
(*I)->dump();
|
|
|
|
cerr << "\n====== End graphs for function `" << method->getName()
|
|
<< "' ========\n\n";
|
|
}
|
|
|
|
|
|
void
|
|
SchedGraphSet::buildGraphsForMethod(const Function *F,
|
|
const TargetMachine& target)
|
|
{
|
|
for (Function::const_iterator BI = F->begin(); BI != F->end(); ++BI)
|
|
addGraph(new SchedGraph(*BI, target));
|
|
}
|
|
|
|
|
|
std::ostream &operator<<(std::ostream &os, const SchedGraphEdge& edge)
|
|
{
|
|
os << "edge [" << edge.src->getNodeId() << "] -> ["
|
|
<< edge.sink->getNodeId() << "] : ";
|
|
|
|
switch(edge.depType) {
|
|
case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break;
|
|
case SchedGraphEdge::ValueDep: os<< "Reg Value " << edge.val; break;
|
|
case SchedGraphEdge::MemoryDep: os<< "Memory Dep"; break;
|
|
case SchedGraphEdge::MachineRegister: os<< "Reg " <<edge.machineRegNum;break;
|
|
case SchedGraphEdge::MachineResource: os<<"Resource "<<edge.resourceId;break;
|
|
default: assert(0); break;
|
|
}
|
|
|
|
os << " : delay = " << edge.minDelay << "\n";
|
|
|
|
return os;
|
|
}
|
|
|
|
std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node)
|
|
{
|
|
os << std::string(8, ' ')
|
|
<< "Node " << node.nodeId << " : "
|
|
<< "latency = " << node.latency << "\n" << std::string(12, ' ');
|
|
|
|
if (node.getMachineInstr() == NULL)
|
|
os << "(Dummy node)\n";
|
|
else
|
|
{
|
|
os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
|
|
os << node.inEdges.size() << " Incoming Edges:\n";
|
|
for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
|
|
os << std::string(16, ' ') << *node.inEdges[i];
|
|
|
|
os << std::string(12, ' ') << node.outEdges.size()
|
|
<< " Outgoing Edges:\n";
|
|
for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
|
|
os << std::string(16, ' ') << *node.outEdges[i];
|
|
}
|
|
|
|
return os;
|
|
}
|