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f7e042324a
Refactoring; no functional changes intended
Removed PostRAScheduler bits from subtargets (X86, ARM).
Added PostRAScheduler bit to MCSchedModel class.
This bit is set by a CPU's scheduling model (if it exists).
Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses.
Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!).
Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling.
Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values.
Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86:
a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget.
b. MIPS overrides the CPU's postRA settings by enabling postRA for everything.
c. PPC overrides the CPU's postRA settings by enabling postRA for everything.
d. X86 is the only target that actually has postRA specified via sched model info.
Differential Revision: http://reviews.llvm.org/D4217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213101 91177308-0d34-0410-b5e6-96231b3b80d8
62 lines
2.0 KiB
C++
62 lines
2.0 KiB
C++
//===-- TargetSubtargetInfo.cpp - General Target Information ---------------==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the general parts of a Subtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/CommandLine.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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//---------------------------------------------------------------------------
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// TargetSubtargetInfo Class
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//
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TargetSubtargetInfo::TargetSubtargetInfo() {}
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TargetSubtargetInfo::~TargetSubtargetInfo() {}
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// Temporary option to compare overall performance change when moving from the
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// SD scheduler to the MachineScheduler pass pipeline. This is convenient for
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// benchmarking during the transition from SD to MI scheduling. Once armv7 makes
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// the switch, it should go away. The normal way to enable/disable the
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// MachineScheduling pass itself is by using -enable-misched. For targets that
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// already use MI sched (via MySubTarget::enableMachineScheduler())
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// -misched-bench=false negates the subtarget hook.
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static cl::opt<bool> BenchMachineSched("misched-bench", cl::Hidden,
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cl::desc("Migrate from the target's default SD scheduler to MI scheduler"));
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bool TargetSubtargetInfo::useMachineScheduler() const {
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if (BenchMachineSched.getNumOccurrences())
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return BenchMachineSched;
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return enableMachineScheduler();
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}
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bool TargetSubtargetInfo::enableAtomicExpandLoadLinked() const {
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return true;
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}
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bool TargetSubtargetInfo::enableMachineScheduler() const {
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return false;
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}
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bool TargetSubtargetInfo::enableRALocalReassignment(
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CodeGenOpt::Level OptLevel) const {
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return true;
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}
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bool TargetSubtargetInfo::enablePostMachineScheduler() const {
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return getSchedModel()->PostRAScheduler;
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}
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bool TargetSubtargetInfo::useAA() const {
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return false;
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}
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