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25ab690a43
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
87 lines
2.6 KiB
C++
Executable File
87 lines
2.6 KiB
C++
Executable File
//===-- X86AsmPrinter.h - Convert X86 LLVM code to Intel assembly ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file the shared super class printer that converts from our internal
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// representation of machine-dependent LLVM code to Intel and AT&T format
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// assembly language. This printer is the output mechanism used by `llc'.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86ASMPRINTER_H
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#define X86ASMPRINTER_H
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#include "X86.h"
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#include "X86TargetMachine.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/DwarfWriter.h"
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#include "llvm/CodeGen/MachineDebugInfo.h"
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#include "llvm/ADT/Statistic.h"
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#include <set>
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namespace llvm {
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extern Statistic<> EmittedInsts;
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// FIXME: Move this to CodeGen/AsmPrinter.h
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namespace PICStyle {
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enum X86AsmPICStyle {
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Stub, GOT
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};
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}
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struct VISIBILITY_HIDDEN X86SharedAsmPrinter : public AsmPrinter {
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DwarfWriter DW;
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X86SharedAsmPrinter(std::ostream &O, X86TargetMachine &TM,
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const TargetAsmInfo *T)
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: AsmPrinter(O, TM, T), DW(O, this, T), X86PICStyle(PICStyle::GOT) {
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Subtarget = &TM.getSubtarget<X86Subtarget>();
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}
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bool doInitialization(Module &M);
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bool doFinalization(Module &M);
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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if (Subtarget->isTargetDarwin()) {
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AU.addRequired<MachineDebugInfo>();
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}
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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PICStyle::X86AsmPICStyle X86PICStyle;
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const X86Subtarget *Subtarget;
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// Necessary for Darwin to print out the apprioriate types of linker stubs
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std::set<std::string> FnStubs, GVStubs, LinkOnceStubs;
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inline static bool isScale(const MachineOperand &MO) {
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return MO.isImmediate() &&
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(MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
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MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
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}
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inline static bool isMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFrameIndex()) return true;
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return Op+4 <= MI->getNumOperands() &&
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MI->getOperand(Op ).isRegister() && isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isRegister() &&
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(MI->getOperand(Op+3).isImmediate() ||
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MI->getOperand(Op+3).isGlobalAddress() ||
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MI->getOperand(Op+3).isConstantPoolIndex() ||
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MI->getOperand(Op+3).isJumpTableIndex());
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}
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};
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} // end namespace llvm
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#endif
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