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subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
152 lines
5.5 KiB
C++
152 lines
5.5 KiB
C++
//===- CodeGenSchedule.cpp - Scheduling MachineModels ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines structures to encapsulate the machine model as decribed in
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// the target description.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "subtarget-emitter"
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#include "CodeGenSchedule.h"
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#include "CodeGenTarget.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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// CodeGenModels ctor interprets machine model records and populates maps.
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CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK,
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const CodeGenTarget &TGT):
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Records(RK), Target(TGT), NumItineraryClasses(0), HasProcItineraries(false) {
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// Populate SchedClassIdxMap and set NumItineraryClasses.
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CollectSchedClasses();
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// Populate ProcModelMap.
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CollectProcModels();
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}
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// Visit all the instruction definitions for this target to gather and enumerate
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// the itinerary classes. These are the explicitly specified SchedClasses. More
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// SchedClasses may be inferred.
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void CodeGenSchedModels::CollectSchedClasses() {
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// NoItinerary is always the first class at Index=0
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SchedClasses.resize(1);
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SchedClasses.back().Name = "NoItinerary";
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SchedClassIdxMap[SchedClasses.back().Name] = 0;
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// Gather and sort all itinerary classes used by instruction descriptions.
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std::vector<Record*> ItinClassList;
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for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
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E = Target.inst_end(); I != E; ++I) {
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Record *SchedDef = (*I)->TheDef->getValueAsDef("Itinerary");
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// Map a new SchedClass with no index.
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if (!SchedClassIdxMap.count(SchedDef->getName())) {
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SchedClassIdxMap[SchedDef->getName()] = 0;
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ItinClassList.push_back(SchedDef);
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}
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}
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// Assign each itinerary class unique number, skipping NoItinerary==0
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NumItineraryClasses = ItinClassList.size();
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std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord());
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for (unsigned i = 0, N = NumItineraryClasses; i < N; i++) {
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Record *ItinDef = ItinClassList[i];
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SchedClassIdxMap[ItinDef->getName()] = SchedClasses.size();
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SchedClasses.push_back(CodeGenSchedClass(ItinDef));
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}
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// TODO: Infer classes from non-itinerary scheduler resources.
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}
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// Gather all processor models.
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void CodeGenSchedModels::CollectProcModels() {
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std::vector<Record*> ProcRecords =
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Records.getAllDerivedDefinitions("Processor");
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std::sort(ProcRecords.begin(), ProcRecords.end(), LessRecordFieldName());
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// Reserve space because we can. Reallocation would be ok.
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ProcModels.reserve(ProcRecords.size());
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// For each processor, find a unique machine model.
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for (unsigned i = 0, N = ProcRecords.size(); i < N; ++i)
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addProcModel(ProcRecords[i]);
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}
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// Get a unique processor model based on the defined MachineModel and
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// ProcessorItineraries.
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void CodeGenSchedModels::addProcModel(Record *ProcDef) {
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unsigned Idx = getProcModelIdx(ProcDef);
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if (Idx < ProcModels.size())
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return;
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Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
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Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
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std::string ModelName = ModelDef->getName();
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const std::string &ItinName = ItinsDef->getName();
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bool NoModel = ModelDef->getValueAsBit("NoModel");
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bool hasTopLevelItin = !ItinsDef->getValueAsListOfDefs("IID").empty();
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if (NoModel) {
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// If an itinerary is defined without a machine model, infer a new model.
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if (NoModel && hasTopLevelItin) {
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ModelName = ItinName + "Model";
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ModelDef = NULL;
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}
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}
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else {
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// If a machine model is defined, the itinerary must be defined within it
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// rather than in the Processor definition itself.
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assert(!hasTopLevelItin && "Itinerary must be defined in SchedModel");
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ItinsDef = ModelDef->getValueAsDef("Itineraries");
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}
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ProcModelMap[getProcModelKey(ProcDef)]= ProcModels.size();
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ProcModels.push_back(CodeGenProcModel(ModelName, ModelDef, ItinsDef));
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std::vector<Record*> ItinRecords = ItinsDef->getValueAsListOfDefs("IID");
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CollectProcItin(ProcModels.back(), ItinRecords);
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}
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// Gather the processor itineraries.
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void CodeGenSchedModels::CollectProcItin(CodeGenProcModel &ProcModel,
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std::vector<Record*> ItinRecords) {
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// Skip empty itinerary.
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if (ItinRecords.empty())
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return;
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HasProcItineraries = true;
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ProcModel.ItinDefList.resize(NumItineraryClasses+1);
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// Insert each itinerary data record in the correct position within
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// the processor model's ItinDefList.
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for (unsigned i = 0, N = ItinRecords.size(); i < N; i++) {
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Record *ItinData = ItinRecords[i];
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Record *ItinDef = ItinData->getValueAsDef("TheClass");
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if (!SchedClassIdxMap.count(ItinDef->getName())) {
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DEBUG(dbgs() << ProcModel.ItinsDef->getName()
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<< " has unused itinerary class " << ItinDef->getName() << '\n');
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continue;
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}
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ProcModel.ItinDefList[getItinClassIdx(ItinDef)] = ItinData;
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}
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#ifndef NDEBUG
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// Check for missing itinerary entries.
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assert(!ProcModel.ItinDefList[0] && "NoItinerary class can't have rec");
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for (unsigned i = 1, N = ProcModel.ItinDefList.size(); i < N; ++i) {
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if (!ProcModel.ItinDefList[i])
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DEBUG(dbgs() << ProcModel.ItinsDef->getName()
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<< " missing itinerary for class " << SchedClasses[i].Name << '\n');
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}
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#endif
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}
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