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subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
173 lines
5.7 KiB
C++
173 lines
5.7 KiB
C++
//===- CodeGenSchedule.h - Scheduling Machine Models ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines structures to encapsulate the machine model as decribed in
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// the target description.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CODEGEN_SCHEDULE_H
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#define CODEGEN_SCHEDULE_H
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#include "llvm/TableGen/Record.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/StringMap.h"
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namespace llvm {
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class CodeGenTarget;
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// Scheduling class.
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//
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// Each instruction description will be mapped to a scheduling class. It may be
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// an explicitly defined itinerary class, or an inferred class in which case
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// ItinClassDef == NULL.
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struct CodeGenSchedClass {
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std::string Name;
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unsigned Index;
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Record *ItinClassDef;
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CodeGenSchedClass(): Index(0), ItinClassDef(0) {}
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CodeGenSchedClass(Record *rec): Index(0), ItinClassDef(rec) {
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Name = rec->getName();
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}
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};
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// Processor model.
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//
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// ModelName is a unique name used to name an instantiation of MCSchedModel.
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//
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// ModelDef is NULL for inferred Models. This happens when a processor defines
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// an itinerary but no machine model. If the processer defines neither a machine
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// model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has
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// the special "NoModel" field set to true.
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//
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// ItinsDef always points to a valid record definition, but may point to the
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// default NoItineraries. NoItineraries has an empty list of InstrItinData
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// records.
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//
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// ItinDefList orders this processor's InstrItinData records by SchedClass idx.
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struct CodeGenProcModel {
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std::string ModelName;
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Record *ModelDef;
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Record *ItinsDef;
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// Array of InstrItinData records indexed by CodeGenSchedClass::Index.
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// The list is empty if the subtarget has no itineraries.
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std::vector<Record *> ItinDefList;
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CodeGenProcModel(const std::string &Name, Record *MDef, Record *IDef):
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ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {}
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};
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// Top level container for machine model data.
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class CodeGenSchedModels {
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RecordKeeper &Records;
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const CodeGenTarget &Target;
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// List of unique SchedClasses.
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std::vector<CodeGenSchedClass> SchedClasses;
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// Map SchedClass name to itinerary index.
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// These are either explicit itinerary classes or inferred classes.
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StringMap<unsigned> SchedClassIdxMap;
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// SchedClass indices 1 up to and including NumItineraryClasses identify
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// itinerary classes that are explicitly used for this target's instruction
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// definitions. NoItinerary always has index 0 regardless of whether it is
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// explicitly referenced.
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//
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// Any inferred SchedClass have a index greater than NumItineraryClasses.
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unsigned NumItineraryClasses;
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// List of unique processor models.
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std::vector<CodeGenProcModel> ProcModels;
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// Map Processor's MachineModel + ProcItin fields to a CodeGenProcModel index.
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typedef DenseMap<std::pair<Record*, Record*>, unsigned> ProcModelMapTy;
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ProcModelMapTy ProcModelMap;
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// True if any processors have nonempty itineraries.
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bool HasProcItineraries;
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public:
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CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
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// Check if any instructions are assigned to an explicit itinerary class other
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// than NoItinerary.
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bool hasItineraryClasses() const { return NumItineraryClasses > 0; }
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// Return the number of itinerary classes in use by this target's instruction
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// descriptions, not including "NoItinerary".
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unsigned numItineraryClasses() const {
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return NumItineraryClasses;
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}
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// Get a SchedClass from its index.
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const CodeGenSchedClass &getSchedClass(unsigned Idx) {
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assert(Idx < SchedClasses.size() && "bad SchedClass index");
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return SchedClasses[Idx];
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}
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// Get an itinerary class's index. Value indices are '0' for NoItinerary up to
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// and including numItineraryClasses().
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unsigned getItinClassIdx(Record *ItinDef) const {
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assert(SchedClassIdxMap.count(ItinDef->getName()) && "missing ItinClass");
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unsigned Idx = SchedClassIdxMap.lookup(ItinDef->getName());
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assert(Idx <= NumItineraryClasses && "bad ItinClass index");
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return Idx;
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}
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bool hasProcessorItineraries() const {
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return HasProcItineraries;
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}
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// Get an existing machine model for a processor definition.
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const CodeGenProcModel &getProcModel(Record *ProcDef) const {
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unsigned idx = getProcModelIdx(ProcDef);
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assert(idx < ProcModels.size() && "missing machine model");
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return ProcModels[idx];
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}
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// Iterate over the unique processor models.
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typedef std::vector<CodeGenProcModel>::const_iterator ProcIter;
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ProcIter procModelBegin() const { return ProcModels.begin(); }
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ProcIter procModelEnd() const { return ProcModels.end(); }
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private:
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// Get a key that can uniquely identify a machine model.
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ProcModelMapTy::key_type getProcModelKey(Record *ProcDef) const {
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Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
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Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
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return std::make_pair(ModelDef, ItinsDef);
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}
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// Get the unique index of a machine model.
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unsigned getProcModelIdx(Record *ProcDef) const {
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ProcModelMapTy::const_iterator I =
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ProcModelMap.find(getProcModelKey(ProcDef));
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if (I == ProcModelMap.end())
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return ProcModels.size();
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return I->second;
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}
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// Initialize a new processor model if it is unique.
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void addProcModel(Record *ProcDef);
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void CollectSchedClasses();
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void CollectProcModels();
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void CollectProcItin(CodeGenProcModel &ProcModel,
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std::vector<Record*> ItinRecords);
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};
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} // namespace llvm
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#endif
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