mirror of
https://github.com/c64scene-ar/llvm-6502.git
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dca6cdd6a1
Stefanovic. I removed the part that actually emits the instructions cause I want that to get in better shape first and in incremental steps. This also makes it easier to review the upcoming parts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135678 91177308-0d34-0410-b5e6-96231b3b80d8
93 lines
3.1 KiB
C++
93 lines
3.1 KiB
C++
//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Mips target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "MipsTargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeMipsTarget() {
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// Register the target.
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RegisterTargetMachine<MipsTargetMachine> X(TheMipsTarget);
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RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
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}
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// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
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// The stack is always 8 byte aligned
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// On function prologue, the stack is created by decrementing
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// its pointer. Once decremented, all references are done with positive
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// offset from the stack/frame pointer, using StackGrowsUp enables
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// an easier handling.
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// Using CodeModel::Large enables different CALL behavior.
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MipsTargetMachine::
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MipsTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM,
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bool isLittle=false):
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LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
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Subtarget(TT, CPU, FS, isLittle),
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DataLayout(isLittle ?
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std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
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std::string("E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
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InstrInfo(*this),
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FrameLowering(Subtarget),
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TLInfo(*this), TSInfo(*this), JITInfo() {
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}
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MipselTargetMachine::
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MipselTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM) :
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MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {}
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// Install an instruction selector pass using
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// the ISelDag to gen Mips code.
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bool MipsTargetMachine::
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addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
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{
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PM.add(createMipsISelDag(*this));
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return false;
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}
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted. return true if -print-machineinstrs should
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// print out the code after the passes.
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bool MipsTargetMachine::
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addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
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{
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PM.add(createMipsDelaySlotFillerPass(*this));
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return true;
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}
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bool MipsTargetMachine::
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addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
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PM.add(createMipsEmitGPRestorePass(*this));
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return true;
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}
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bool MipsTargetMachine::
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addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
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PM.add(createMipsExpandPseudoPass(*this));
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return true;
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}
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bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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JITCodeEmitter &JCE) {
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// Machine code emitter pass for Mips.
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PM.add(createMipsJITCodeEmitterPass(*this, JCE));
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return false;
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}
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