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adf1668bec
llvm-6502/test/CodeGen
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Adam Nemet adf1668bec [ARM64] PR19792: Fix cycle in DAG after performPostLD1Combine 
Povray and dealII currently assert with "Overran sorted position" in
AssignTopologicalOrder.  The problem is that performPostLD1Combine can
introduce cycles.

Consider:

(insert_vector_elt (INSERT_SUBREG undef,
                                  (load (add %vreg0, Constant<8>), undef),  <= A
                                  TargetConstant<2>),
                   (load %vreg0, undef),                                    <= B
                   Constant<1>)

This is turned into a LD1LANEpost node.  However the address in A is not a
valid user of the post-incremented address of B in LD1LANEpost.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209242 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-20 21:47:07 +00:00
..
AArch64 Revert "Implement global merge optimization for global variables." 2014-05-16 13:02:18 +00:00
ARM SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the bswap not. 2014-05-19 13:12:38 +00:00
ARM64 [ARM64] PR19792: Fix cycle in DAG after performPostLD1Combine 2014-05-20 21:47:07 +00:00
CPP
Generic
Hexagon reverting r209132 2014-05-19 16:22:11 +00:00
Inputs
Mips Finish materialize for ints 2014-05-15 21:54:15 +00:00
MSP430
NVPTX
PowerPC [PowerPC] PR19796: Also match ISD::TargetConstant in isIntS16Immediate 2014-05-20 17:20:34 +00:00
R600 R600/SI: Promote f32 SELECT to i32 2014-05-16 20:56:41 +00:00
SPARC TableGen: fix operand counting for aliases 2014-05-16 09:42:04 +00:00
SystemZ
Thumb Re-enable inline memcpy expansion for Thumb1. 2014-05-16 14:24:22 +00:00
Thumb2 Fix the Load/Store optimization pass to work with Thumb1. 2014-05-16 14:14:30 +00:00
X86 Move the function and data section flags into the options struct and 2014-05-20 21:25:34 +00:00
XCore