mirror of
https://github.com/c64scene-ar/llvm-6502.git
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86245071b5
Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
132 lines
5.9 KiB
LLVM
132 lines
5.9 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
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;CHECK-DAG: IMAGE_LOAD {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, -1
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;CHECK-DAG: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 2, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 1, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 4, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 8, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 5, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 12, 0, 0, -1
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;CHECK-DAG: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 7, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 8, 0, 0, -1
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define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
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%v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
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%v2 = insertelement <4 x i32> undef, i32 %a1, i32 1
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%v3 = insertelement <4 x i32> undef, i32 %a1, i32 2
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%v4 = insertelement <4 x i32> undef, i32 %a1, i32 3
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%v5 = insertelement <4 x i32> undef, i32 %a2, i32 0
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%v6 = insertelement <4 x i32> undef, i32 %a2, i32 1
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%v10 = insertelement <4 x i32> undef, i32 %a3, i32 1
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%v11 = insertelement <4 x i32> undef, i32 %a3, i32 2
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%v15 = insertelement <4 x i32> undef, i32 %a4, i32 2
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%v16 = insertelement <4 x i32> undef, i32 %a4, i32 3
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%res1 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v1,
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<32 x i8> undef, i32 1)
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%res2 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v2,
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<32 x i8> undef, i32 2)
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%res3 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v3,
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<32 x i8> undef, i32 3)
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%res4 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v4,
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<32 x i8> undef, i32 4)
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%res5 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v5,
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<32 x i8> undef, i32 5)
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%res6 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v6,
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<32 x i8> undef, i32 6)
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%res10 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v10,
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<32 x i8> undef, i32 10)
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%res11 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v11,
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<32 x i8> undef, i32 11)
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%res15 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v15,
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<32 x i8> undef, i32 15)
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%res16 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v16,
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<32 x i8> undef, i32 16)
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%e1 = extractelement <4 x i32> %res1, i32 0
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%e2 = extractelement <4 x i32> %res2, i32 1
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%e3 = extractelement <4 x i32> %res3, i32 2
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%e4 = extractelement <4 x i32> %res4, i32 3
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%t0 = extractelement <4 x i32> %res5, i32 0
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%t1 = extractelement <4 x i32> %res5, i32 1
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%e5 = add i32 %t0, %t1
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%t2 = extractelement <4 x i32> %res6, i32 0
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%t3 = extractelement <4 x i32> %res6, i32 2
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%e6 = add i32 %t2, %t3
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%t10 = extractelement <4 x i32> %res10, i32 2
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%t11 = extractelement <4 x i32> %res10, i32 3
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%e10 = add i32 %t10, %t11
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%t12 = extractelement <4 x i32> %res11, i32 0
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%t13 = extractelement <4 x i32> %res11, i32 1
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%t14 = extractelement <4 x i32> %res11, i32 2
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%t15 = add i32 %t12, %t13
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%e11 = add i32 %t14, %t15
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%t28 = extractelement <4 x i32> %res15, i32 0
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%t29 = extractelement <4 x i32> %res15, i32 1
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%t30 = extractelement <4 x i32> %res15, i32 2
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%t31 = extractelement <4 x i32> %res15, i32 3
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%t32 = add i32 %t28, %t29
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%t33 = add i32 %t30, %t31
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%e15 = add i32 %t32, %t33
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%e16 = extractelement <4 x i32> %res16, i32 3
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%s1 = add i32 %e1, %e2
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%s2 = add i32 %s1, %e3
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%s3 = add i32 %s2, %e4
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%s4 = add i32 %s3, %e5
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%s5 = add i32 %s4, %e6
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%s9 = add i32 %s5, %e10
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%s10 = add i32 %s9, %e11
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%s14 = add i32 %s10, %e15
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%s15 = add i32 %s14, %e16
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%s16 = bitcast i32 %s15 to float
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %s16, float %s16, float %s16, float %s16)
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ret void
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}
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; Test that ccordinates are stored in vgprs and not sgprs
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; CHECK: vgpr_coords
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; CHECK: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}
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define void @vgpr_coords(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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%20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0
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%21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !2
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%22 = getelementptr float addrspace(2)* %21, i32 0
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%23 = load float addrspace(2)* %22, !tbaa !2, !invariant.load !1
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%24 = getelementptr float addrspace(2)* %21, i32 1
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%25 = load float addrspace(2)* %24, !tbaa !2, !invariant.load !1
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%26 = getelementptr float addrspace(2)* %21, i32 4
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%27 = load float addrspace(2)* %26, !tbaa !2, !invariant.load !1
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%28 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
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%29 = load <32 x i8> addrspace(2)* %28, !tbaa !2
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%30 = bitcast float %27 to i32
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%31 = bitcast float %23 to i32
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%32 = bitcast float %25 to i32
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%33 = insertelement <4 x i32> undef, i32 %31, i32 0
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%34 = insertelement <4 x i32> %33, i32 %32, i32 1
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%35 = insertelement <4 x i32> %34, i32 %30, i32 2
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%36 = insertelement <4 x i32> %35, i32 undef, i32 3
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%37 = call <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32> %36, <32 x i8> %29, i32 2)
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%38 = extractelement <4 x i32> %37, i32 0
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%39 = extractelement <4 x i32> %37, i32 1
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%40 = extractelement <4 x i32> %37, i32 2
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%41 = extractelement <4 x i32> %37, i32 3
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%42 = bitcast i32 %38 to float
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%43 = bitcast i32 %39 to float
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%44 = bitcast i32 %40 to float
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%45 = bitcast i32 %41 to float
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %42, float %43, float %44, float %45)
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ret void
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}
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declare <4 x i32> @llvm.SI.imageload.(<4 x i32>, <32 x i8>, i32) readnone
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32>, <32 x i8>, i32) #1
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { "ShaderType"="0" }
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attributes #1 = { nounwind readnone }
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!0 = metadata !{metadata !"const", null}
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!1 = metadata !{}
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!2 = metadata !{metadata !0, metadata !0, i64 0, i32 1}
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