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b0f8afd43c
The assertion was checking that the virtual register VReg used to represent the physical register PReg uses the same register class as the one passed to MachineFunction::addLiveIn. This is over-constraining because it is sufficient to check that the register class of VReg (VRegRC) is a subclass of the register class of PReg (PRegRC) and that VRegRC contains PReg. Indeed, if VReg gets constrained because of some operation constraints between two calls of MachineFunction::addLiveIn, the original assertion cannot match. This fixes <rdar://problem/15633429>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197097 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
679 B
LLVM
25 lines
679 B
LLVM
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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; Test case related to <rdar://problem/15633429>.
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; CHECK-LABEL: small
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define i64 @small(i64 %encodedBase) {
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cmp:
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%lnot.i.i = icmp eq i64 %encodedBase, 0
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br i1 %lnot.i.i, label %if, label %else
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if:
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%tmp1 = call i8* @llvm.returnaddress(i32 0)
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br label %end
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else:
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%tmp3 = call i8* @llvm.returnaddress(i32 0)
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%ptr = getelementptr inbounds i8* %tmp3, i64 -16
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%ld = load i8* %ptr, align 4
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%tmp2 = inttoptr i8 %ld to i8*
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br label %end
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end:
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%tmp = phi i8* [ %tmp1, %if ], [ %tmp2, %else ]
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%coerce.val.pi56 = ptrtoint i8* %tmp to i64
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ret i64 %coerce.val.pi56
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}
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declare i8* @llvm.returnaddress(i32)
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