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https://github.com/c64scene-ar/llvm-6502.git
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87773c318f
Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
2.5 KiB
LLVM
57 lines
2.5 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>)
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declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>)
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declare <2 x i64> @llvm.aarch64.neon.vacgeq(<2 x double>, <2 x double>)
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define <2 x i32> @facge_from_intr_v2i32(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
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; Using registers other than v0, v1 and v2 are possible, but would be odd.
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; CHECK: facge_from_intr_v2i32:
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%val = call <2 x i32> @llvm.arm.neon.vacged(<2 x float> %A, <2 x float> %B)
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; CHECK: facge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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ret <2 x i32> %val
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}
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define <4 x i32> @facge_from_intr_v4i32( <4 x float> %A, <4 x float> %B) {
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; Using registers other than v0, v1 and v2 are possible, but would be odd.
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; CHECK: facge_from_intr_v4i32:
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%val = call <4 x i32> @llvm.arm.neon.vacgeq(<4 x float> %A, <4 x float> %B)
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; CHECK: facge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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ret <4 x i32> %val
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}
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define <2 x i64> @facge_from_intr_v2i64(<2 x double> %A, <2 x double> %B) {
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; Using registers other than v0, v1 and v2 are possible, but would be odd.
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; CHECK: facge_from_intr_v2i64:
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%val = call <2 x i64> @llvm.aarch64.neon.vacgeq(<2 x double> %A, <2 x double> %B)
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; CHECK: facge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
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ret <2 x i64> %val
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}
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declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>)
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declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>)
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declare <2 x i64> @llvm.aarch64.neon.vacgtq(<2 x double>, <2 x double>)
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define <2 x i32> @facgt_from_intr_v2i32(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
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; Using registers other than v0, v1 and v2 are possible, but would be odd.
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; CHECK: facgt_from_intr_v2i32:
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%val = call <2 x i32> @llvm.arm.neon.vacgtd(<2 x float> %A, <2 x float> %B)
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; CHECK: facgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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ret <2 x i32> %val
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}
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define <4 x i32> @facgt_from_intr_v4i32( <4 x float> %A, <4 x float> %B) {
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; Using registers other than v0, v1 and v2 are possible, but would be odd.
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; CHECK: facgt_from_intr_v4i32:
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%val = call <4 x i32> @llvm.arm.neon.vacgtq(<4 x float> %A, <4 x float> %B)
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; CHECK: facgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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ret <4 x i32> %val
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}
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define <2 x i64> @facgt_from_intr_v2i64(<2 x double> %A, <2 x double> %B) {
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; Using registers other than v0, v1 and v2 are possible, but would be odd.
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; CHECK: facgt_from_intr_v2i64:
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%val = call <2 x i64> @llvm.aarch64.neon.vacgtq(<2 x double> %A, <2 x double> %B)
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; CHECK: facgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
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ret <2 x i64> %val
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}
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