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2f21452ba1
When generating the IfTrue basic block during the F128CSEL pseudo-instruction handling, the NZCV live-in for the newly created BB wasn't being added. This caused a fault during MI-sched/live range calculation when the predecessor for the fall-through BB didn't have a live-in for phys-reg as expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193316 91177308-0d34-0410-b5e6-96231b3b80d8
18 lines
527 B
LLVM
18 lines
527 B
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s
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; Regression test for NZCV reg live-in not being added to fp128csel IfTrue BB,
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; causing a crash during live range calc.
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define void @fp128_livein(i64 %a) {
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%tobool = icmp ne i64 %a, 0
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%conv = zext i1 %tobool to i32
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%conv2 = sitofp i32 %conv to fp128
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%conv6 = sitofp i32 %conv to double
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%call3 = tail call i32 @g(fp128 %conv2)
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%call8 = tail call i32 @h(double %conv6)
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ret void
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}
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declare i32 @f()
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declare i32 @g(fp128)
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declare i32 @h(double)
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