mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-04 22:29:22 +00:00
922d314e8f
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
2.1 KiB
LLVM
56 lines
2.1 KiB
LLVM
; RUN: llc -mcpu=generic -mtriple=i386-apple-darwin -tailcallopt < %s | FileCheck %s
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; Check that lowered argumens do not overwrite the return address before it is moved.
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; Bug 6225
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;
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; If a call is a fastcc tail call and tail call optimization is enabled, the
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; caller frame is replaced by the callee frame. This can require that arguments are
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; placed on the former return address stack slot. Special care needs to be taken
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; taken that the return address is moved / or stored in a register before
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; lowering of arguments potentially overwrites the value.
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;
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; Move return address (76(%esp)) to a temporary register (%ebp)
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; CHECK: movl 76(%esp), [[REGISTER:%[a-z]+]]
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; Overwrite return addresss
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; CHECK: movl [[EBX:%[a-z]+]], 76(%esp)
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; Move return address from temporary register (%ebp) to new stack location (60(%esp))
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; CHECK: movl [[REGISTER]], 60(%esp)
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%tupl_p = type [9 x i32]*
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declare fastcc void @l297(i32 %r10, i32 %r9, i32 %r8, i32 %r7, i32 %r6, i32 %r5, i32 %r3, i32 %r2) noreturn nounwind
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declare fastcc void @l298(i32 %r10, i32 %r9, i32 %r4) noreturn nounwind
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define fastcc void @l186(%tupl_p %r1) noreturn nounwind {
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entry:
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%ptr1 = getelementptr %tupl_p %r1, i32 0, i32 0
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%r2 = load i32* %ptr1
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%ptr3 = getelementptr %tupl_p %r1, i32 0, i32 1
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%r3 = load i32* %ptr3
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%ptr5 = getelementptr %tupl_p %r1, i32 0, i32 2
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%r4 = load i32* %ptr5
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%ptr7 = getelementptr %tupl_p %r1, i32 0, i32 3
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%r5 = load i32* %ptr7
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%ptr9 = getelementptr %tupl_p %r1, i32 0, i32 4
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%r6 = load i32* %ptr9
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%ptr11 = getelementptr %tupl_p %r1, i32 0, i32 5
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%r7 = load i32* %ptr11
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%ptr13 = getelementptr %tupl_p %r1, i32 0, i32 6
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%r8 = load i32* %ptr13
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%ptr15 = getelementptr %tupl_p %r1, i32 0, i32 7
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%r9 = load i32* %ptr15
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%ptr17 = getelementptr %tupl_p %r1, i32 0, i32 8
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%r10 = load i32* %ptr17
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%cond = icmp eq i32 %r10, 3
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br i1 %cond, label %true, label %false
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true:
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tail call fastcc void @l297(i32 %r10, i32 %r9, i32 %r8, i32 %r7, i32 %r6, i32 %r5, i32 %r3, i32 %r2) noreturn nounwind
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ret void
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false:
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tail call fastcc void @l298(i32 %r10, i32 %r9, i32 %r4) noreturn nounwind
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ret void
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}
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