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ae1ae2c3a1
Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores. Added SDNodes for masked operations and lowering patterns for X86 code generator. Examples: <16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask) declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask) Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch. http://reviews.llvm.org/D6191 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222632 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
already-vectorized.ll | ||
assume.ll | ||
avx1.ll | ||
avx512.ll | ||
constant-vector-operand.ll | ||
conversion-cost.ll | ||
cost-model.ll | ||
fp32_to_uint32-cost-model.ll | ||
fp64_to_uint32-cost-model.ll | ||
fp_to_sint8-cost-model.ll | ||
gather-cost.ll | ||
gcc-examples.ll | ||
illegal-parallel-loop-uniform-write.ll | ||
lit.local.cfg | ||
mask1.ll | ||
mask2.ll | ||
mask3.ll | ||
mask4.ll | ||
metadata-enable.ll | ||
min-trip-count-switch.ll | ||
no-vector.ll | ||
parallel-loops-after-reg2mem.ll | ||
parallel-loops.ll | ||
powof2div.ll | ||
rauw-bug.ll | ||
reduction-crash.ll | ||
small-size.ll | ||
struct-store.ll | ||
tripcount.ll | ||
uint64_to_fp64-cost-model.ll | ||
unroll_selection.ll | ||
unroll-pm.ll | ||
unroll-small-loops.ll | ||
vect.omp.force.ll | ||
vect.omp.force.small-tc.ll | ||
vector_ptr_load_store.ll | ||
vector-scalar-select-cost.ll | ||
vectorization-remarks-missed.ll | ||
vectorization-remarks.ll | ||
x86_fp80-vector-store.ll |