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https://github.com/c64scene-ar/llvm-6502.git
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ae3a0be92e
integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
65 lines
2.4 KiB
LLVM
65 lines
2.4 KiB
LLVM
; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca
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; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | grep {load <4 x float>}
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define void @test(<4 x float>* %F, float %f) {
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entry:
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%G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=3]
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%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
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%tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp3, <4 x float>* %G
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%G.upgrd.1 = getelementptr <4 x float>* %G, i32 0, i32 0 ; <float*> [#uses=1]
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store float %f, float* %G.upgrd.1
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%tmp4 = load <4 x float>* %G ; <<4 x float>> [#uses=2]
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%tmp6 = fadd <4 x float> %tmp4, %tmp4 ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp6, <4 x float>* %F
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ret void
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}
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define void @test2(<4 x float>* %F, float %f) {
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entry:
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%G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=3]
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%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
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%tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp3, <4 x float>* %G
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%tmp.upgrd.2 = getelementptr <4 x float>* %G, i32 0, i32 2 ; <float*> [#uses=1]
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store float %f, float* %tmp.upgrd.2
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%tmp4 = load <4 x float>* %G ; <<4 x float>> [#uses=2]
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%tmp6 = fadd <4 x float> %tmp4, %tmp4 ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp6, <4 x float>* %F
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ret void
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}
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define void @test3(<4 x float>* %F, float* %f) {
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entry:
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%G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=2]
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%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
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%tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp3, <4 x float>* %G
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%tmp.upgrd.3 = getelementptr <4 x float>* %G, i32 0, i32 2 ; <float*> [#uses=1]
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%tmp.upgrd.4 = load float* %tmp.upgrd.3 ; <float> [#uses=1]
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store float %tmp.upgrd.4, float* %f
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ret void
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}
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define void @test4(<4 x float>* %F, float* %f) {
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entry:
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%G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=2]
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%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
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%tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp3, <4 x float>* %G
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%G.upgrd.5 = getelementptr <4 x float>* %G, i32 0, i32 0 ; <float*> [#uses=1]
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%tmp.upgrd.6 = load float* %G.upgrd.5 ; <float> [#uses=1]
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store float %tmp.upgrd.6, float* %f
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ret void
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}
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define i32 @test5(float %X) { ;; should turn into bitcast.
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%X_addr = alloca [4 x float]
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%X1 = getelementptr [4 x float]* %X_addr, i32 0, i32 2
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store float %X, float* %X1
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%a = bitcast float* %X1 to i32*
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%tmp = load i32* %a
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ret i32 %tmp
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}
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