Evan Cheng ae3ecf9603 Look for SSE and instructions of this form: (and x, (build_vector c1,c2,c3,c4)). ... If there exists a use of a build_vector that's the bitwise complement of the mask, then transform the node to (and (xor x, (build_vector -1,-1,-1,-1)), (build_vector ~c1,~c2,~c3,~c4)). Since this transformation is only useful when 1) the given build_vector will become a load from constpool, and 2) (and (xor x -1), y) matches to a single instruction, I decided this is appropriate as a x86 specific transformation. rdar://7323335 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96389 91177308-0d34-0410-b5e6-96231b3b80d8		2010-02-16 21:09:44 +00:00
..
Alpha	Delete useless trailing semicolons.	2010-01-05 17:55:26 +00:00
ARM	Fix pr6111: Avoid using the LR register for the target address of an indirect	2010-02-16 17:24:15 +00:00
Blackfin	Teach dag combine to fold the following transformation more aggressively:	2010-01-06 19:38:29 +00:00
CBackend	Eliminate more uses of llvm-as and llvm-dis.	2009-09-09 00:09:15 +00:00
CellSPU	don't let asm-verbose break the check-next lines in these tests.	2010-01-19 06:39:54 +00:00
CPP	fix PR5295 where the .ll parser didn't reject a function after a global	2009-10-25 23:22:50 +00:00
Generic	Preliminary patch to improve dwarf EH generation - Hooks to return Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there	2010-02-15 22:35:59 +00:00
Mips	Delete useless trailing semicolons.	2010-01-05 17:55:26 +00:00
MSP430	Reenable tests	2010-01-15 21:19:26 +00:00
PIC16	emit integer and fp zeros as (e.g.) .byte 0 instead of .space 1,	2010-01-20 07:19:19 +00:00
PowerPC	When save/restoring CR at prolog/epilog, in a large	2010-02-12 21:35:34 +00:00
SPARC	add support for the sparcv9-*-* target triple to turn on	2010-02-04 06:34:01 +00:00
SystemZ	Teach dag combine to fold the following transformation more aggressively:	2010-01-06 19:38:29 +00:00
Thumb	Run the pre-register allocation tail duplication pass by default. Remove	2010-01-16 00:29:50 +00:00
Thumb2	Last week we were generating code with duplicate induction variables in this	2010-02-15 21:56:40 +00:00
X86	Look for SSE and instructions of this form: (and x, (build_vector c1,c2,c3,c4)).	2010-02-16 21:09:44 +00:00
XCore	convert the last 3 targets to use EmitFunctionBody() now that	2010-01-28 06:22:43 +00:00