Duraid Madina ae6dcddcfe fixing divides ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25383 91177308-0d34-0410-b5e6-96231b3b80d8		2006-01-17 01:19:49 +00:00
..
Alpha	fix short immediate loads	2006-01-16 21:41:39 +00:00
CBackend	yet more C++ standards-compliance stuff.	2005-12-27 10:40:34 +00:00
IA64	fixing divides	2006-01-17 01:19:49 +00:00
PowerPC	add notes from my *other* email acct.	2006-01-16 17:58:54 +00:00
Skeleton	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
Sparc	Silly Sparc is big endian. If we have to load args out of incoming stack slots	2006-01-16 01:40:00 +00:00
SparcV8	Silly Sparc is big endian. If we have to load args out of incoming stack slots	2006-01-16 01:40:00 +00:00
SparcV9	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
X86	Added a FIXME comment about why FST is currently flagged to fpGETRESULT.	2006-01-17 00:37:42 +00:00
Makefile
MRegisterInfo.cpp
SubtargetFeature.cpp
Target.td	New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace	2006-01-09 18:28:21 +00:00
TargetData.cpp	Implement a new InvalidateStructLayoutInfo method and add some comments	2006-01-14 00:07:34 +00:00
TargetFrameInfo.cpp
TargetInstrInfo.cpp
TargetMachine.cpp
TargetMachineRegistry.cpp
TargetSchedInfo.cpp
TargetSchedule.td
TargetSelectionDAG.td	bswap implementation	2006-01-14 03:14:10 +00:00
TargetSubtarget.cpp