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https://github.com/c64scene-ar/llvm-6502.git
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b503b49b51
This adds all CodeGen tests for the SystemZ target. This version of the patch incorporates feedback from a review by Sean Silva. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
111 lines
3.0 KiB
LLVM
111 lines
3.0 KiB
LLVM
; Test 128-bit addition in which the second operand is variable.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test register addition.
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define void @f1(i128 *%ptr) {
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; CHECK: f1:
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; CHECK: algr
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; CHECK: alcgr
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; CHECK: br %r14
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%value = load i128 *%ptr
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%add = add i128 %value, %value
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store i128 %add, i128 *%ptr
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ret void
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}
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; Test memory addition with no offset. Making the load of %a volatile
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; should force the memory operand to be %b.
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define void @f2(i128 *%aptr, i64 %addr) {
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; CHECK: f2:
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; CHECK: alg {{%r[0-5]}}, 8(%r3)
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; CHECK: alcg {{%r[0-5]}}, 0(%r3)
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; CHECK: br %r14
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%bptr = inttoptr i64 %addr to i128 *
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%a = load volatile i128 *%aptr
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%b = load i128 *%bptr
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%add = add i128 %a, %b
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store i128 %add, i128 *%aptr
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ret void
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}
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; Test the highest aligned offset that is in range of both ALG and ALCG.
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define void @f3(i128 *%aptr, i64 %base) {
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; CHECK: f3:
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; CHECK: alg {{%r[0-5]}}, 524280(%r3)
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; CHECK: alcg {{%r[0-5]}}, 524272(%r3)
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; CHECK: br %r14
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%addr = add i64 %base, 524272
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%bptr = inttoptr i64 %addr to i128 *
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%a = load volatile i128 *%aptr
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%b = load i128 *%bptr
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%add = add i128 %a, %b
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store i128 %add, i128 *%aptr
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ret void
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}
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; Test the next doubleword up, which requires separate address logic for ALG.
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define void @f4(i128 *%aptr, i64 %base) {
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; CHECK: f4:
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; CHECK: lgr [[BASE:%r[1-5]]], %r3
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; CHECK: agfi [[BASE]], 524288
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; CHECK: alg {{%r[0-5]}}, 0([[BASE]])
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; CHECK: alcg {{%r[0-5]}}, 524280(%r3)
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; CHECK: br %r14
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%addr = add i64 %base, 524280
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%bptr = inttoptr i64 %addr to i128 *
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%a = load volatile i128 *%aptr
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%b = load i128 *%bptr
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%add = add i128 %a, %b
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store i128 %add, i128 *%aptr
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ret void
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}
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; Test the next doubleword after that, which requires separate logic for
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; both instructions. It would be better to create an anchor at 524288
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; that both instructions can use, but that isn't implemented yet.
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define void @f5(i128 *%aptr, i64 %base) {
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; CHECK: f5:
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; CHECK: alg {{%r[0-5]}}, 0({{%r[1-5]}})
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; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
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; CHECK: br %r14
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%addr = add i64 %base, 524288
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%bptr = inttoptr i64 %addr to i128 *
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%a = load volatile i128 *%aptr
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%b = load i128 *%bptr
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%add = add i128 %a, %b
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store i128 %add, i128 *%aptr
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ret void
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}
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; Test the lowest displacement that is in range of both ALG and ALCG.
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define void @f6(i128 *%aptr, i64 %base) {
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; CHECK: f6:
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; CHECK: alg {{%r[0-5]}}, -524280(%r3)
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; CHECK: alcg {{%r[0-5]}}, -524288(%r3)
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; CHECK: br %r14
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%addr = add i64 %base, -524288
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%bptr = inttoptr i64 %addr to i128 *
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%a = load volatile i128 *%aptr
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%b = load i128 *%bptr
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%add = add i128 %a, %b
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store i128 %add, i128 *%aptr
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ret void
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}
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; Test the next doubleword down, which is out of range of the ALCG.
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define void @f7(i128 *%aptr, i64 %base) {
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; CHECK: f7:
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; CHECK: alg {{%r[0-5]}}, -524288(%r3)
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; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
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; CHECK: br %r14
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%addr = add i64 %base, -524296
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%bptr = inttoptr i64 %addr to i128 *
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%a = load volatile i128 *%aptr
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%b = load i128 *%bptr
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%add = add i128 %a, %b
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store i128 %add, i128 *%aptr
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ret void
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}
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