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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56596 91177308-0d34-0410-b5e6-96231b3b80d8
218 lines
7.9 KiB
C++
218 lines
7.9 KiB
C++
//===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a MachineFunction pass which runs after register
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// allocation that turns subreg insert/extract instructions into register
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// copies, as needed. This ensures correct codegen even if the coalescer
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// isn't able to remove all subreg instructions.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "lowersubregs"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Compiler.h"
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using namespace llvm;
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namespace {
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struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
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: public MachineFunctionPass {
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static char ID; // Pass identification, replacement for typeid
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LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
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const char *getPassName() const {
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return "Subregister lowering instruction pass";
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - pass entry point
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bool runOnMachineFunction(MachineFunction&);
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bool LowerExtract(MachineInstr *MI);
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bool LowerInsert(MachineInstr *MI);
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bool LowerSubregToReg(MachineInstr *MI);
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};
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char LowerSubregsInstructionPass::ID = 0;
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}
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FunctionPass *llvm::createLowerSubregsPass() {
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return new LowerSubregsInstructionPass();
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}
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bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
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MachineBasicBlock *MBB = MI->getParent();
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MachineFunction &MF = *MBB->getParent();
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const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
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MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
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MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
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unsigned DstReg = MI->getOperand(0).getReg();
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unsigned SuperReg = MI->getOperand(1).getReg();
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unsigned SubIdx = MI->getOperand(2).getImm();
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unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
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assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
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"Extract supperg source must be a physical register");
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assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
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"Insert destination must be in a physical register");
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DOUT << "subreg: CONVERTING: " << *MI;
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if (SrcReg != DstReg) {
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const TargetRegisterClass *TRC = TRI.getPhysicalRegisterRegClass(DstReg);
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assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) &&
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"Extract subreg and Dst must be of same register class");
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TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
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#ifndef NDEBUG
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MachineBasicBlock::iterator dMI = MI;
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DOUT << "subreg: " << *(--dMI);
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#endif
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}
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DOUT << "\n";
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MBB->erase(MI);
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return true;
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}
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bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
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MachineBasicBlock *MBB = MI->getParent();
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MachineFunction &MF = *MBB->getParent();
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const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
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MI->getOperand(1).isImmediate() &&
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(MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
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MI->getOperand(3).isImmediate() && "Invalid subreg_to_reg");
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unsigned DstReg = MI->getOperand(0).getReg();
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unsigned InsReg = MI->getOperand(2).getReg();
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unsigned SubIdx = MI->getOperand(3).getImm();
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assert(SubIdx != 0 && "Invalid index for insert_subreg");
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unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
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assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
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"Insert destination must be in a physical register");
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assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
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"Inserted value must be in a physical register");
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DOUT << "subreg: CONVERTING: " << *MI;
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if (DstSubReg == InsReg) {
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// No need to insert an identify copy instruction.
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DOUT << "subreg: eliminated!";
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} else {
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// Insert sub-register copy
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const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
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const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
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TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
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#ifndef NDEBUG
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MachineBasicBlock::iterator dMI = MI;
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DOUT << "subreg: " << *(--dMI);
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#endif
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}
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DOUT << "\n";
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MBB->erase(MI);
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return true;
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}
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bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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MachineBasicBlock *MBB = MI->getParent();
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MachineFunction &MF = *MBB->getParent();
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const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
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(MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
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(MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
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MI->getOperand(3).isImmediate() && "Invalid insert_subreg");
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unsigned DstReg = MI->getOperand(0).getReg();
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned InsReg = MI->getOperand(2).getReg();
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unsigned SubIdx = MI->getOperand(3).getImm();
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assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
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assert(SubIdx != 0 && "Invalid index for insert_subreg");
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unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
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assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
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"Insert superreg source must be in a physical register");
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assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
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"Inserted value must be in a physical register");
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DOUT << "subreg: CONVERTING: " << *MI;
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if (DstSubReg == InsReg) {
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// No need to insert an identify copy instruction.
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DOUT << "subreg: eliminated!";
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} else {
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// Insert sub-register copy
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const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
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const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
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TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
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#ifndef NDEBUG
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MachineBasicBlock::iterator dMI = MI;
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DOUT << "subreg: " << *(--dMI);
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#endif
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}
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DOUT << "\n";
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MBB->erase(MI);
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return true;
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}
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/// runOnMachineFunction - Reduce subregister inserts and extracts to register
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/// copies.
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///
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bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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DOUT << "Machine Function\n";
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bool MadeChange = false;
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DOUT << "********** LOWERING SUBREG INSTRS **********\n";
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DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
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for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
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mbbi != mbbe; ++mbbi) {
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for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
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mi != me;) {
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MachineInstr *MI = mi++;
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if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
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MadeChange |= LowerExtract(MI);
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} else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
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MadeChange |= LowerInsert(MI);
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} else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
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MadeChange |= LowerSubregToReg(MI);
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}
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}
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}
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return MadeChange;
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}
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