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https://github.com/c64scene-ar/llvm-6502.git
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d8149c1bef
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
24 lines
898 B
LLVM
24 lines
898 B
LLVM
; RUN: llc < %s -march=ptx32 -mattr=sm20 | FileCheck %s
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%complex = type { float, float }
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define ptx_device %complex @complex_add(%complex %a, %complex %b) {
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entry:
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; CHECK: ld.param.f32 r[[R0:[0-9]+]], [__param_1];
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; CHECK-NEXT: ld.param.f32 r[[R2:[0-9]+]], [__param_3];
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; CHECK-NEXT: ld.param.f32 r[[R1:[0-9]+]], [__param_2];
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; CHECK-NEXT: ld.param.f32 r[[R3:[0-9]+]], [__param_4];
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; CHECK-NEXT: add.rn.f32 r[[R0]], r[[R0]], r[[R2]];
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; CHECK-NEXT: add.rn.f32 r[[R1]], r[[R1]], r[[R3]];
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; CHECK-NEXT: ret;
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%a.real = extractvalue %complex %a, 0
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%a.imag = extractvalue %complex %a, 1
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%b.real = extractvalue %complex %b, 0
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%b.imag = extractvalue %complex %b, 1
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%ret.real = fadd float %a.real, %b.real
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%ret.imag = fadd float %a.imag, %b.imag
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%ret.0 = insertvalue %complex undef, float %ret.real, 0
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%ret.1 = insertvalue %complex %ret.0, float %ret.imag, 1
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ret %complex %ret.1
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}
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