llvm-6502/test/CodeGen/Thumb2/ldr-str-imm12.ll
Jakob Stoklund Olesen 0a074ed3ef Switch ARM to using AltOrders instead of MethodBodies.
This slightly changes the GPR allocation order on Darwin where R9 is not
a callee-saved register:

Before: %R0 %R1 %R2 %R3 %R12 %R9 %LR %R4 %R5 %R6 %R8 %R10 %R11
After:  %R0 %R1 %R2 %R3 %R9 %R12 %LR %R4 %R5 %R6 %R8 %R10 %R11

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133326 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18 01:14:46 +00:00

77 lines
3.3 KiB
LLVM

; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim -regalloc=linearscan | FileCheck %s
; rdar://7352504
; Make sure we use "str r9, [sp, #+28]" instead of "sub.w r4, r7, #256" followed by "str r9, [r4, #-32]".
%0 = type { i16, i8, i8 }
%1 = type { [2 x i32], [2 x i32] }
%2 = type { %union.rec* }
%struct.FILE_POS = type { i8, i8, i16, i32 }
%struct.GAP = type { i8, i8, i16 }
%struct.LIST = type { %union.rec*, %union.rec* }
%struct.STYLE = type { %union.anon, %union.anon, i16, i16, i32 }
%struct.head_type = type { [2 x %struct.LIST], %union.FIRST_UNION, %union.SECOND_UNION, %union.THIRD_UNION, %union.FOURTH_UNION, %union.rec*, %2, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, i32 }
%union.FIRST_UNION = type { %struct.FILE_POS }
%union.FOURTH_UNION = type { %struct.STYLE }
%union.SECOND_UNION = type { %0 }
%union.THIRD_UNION = type { %1 }
%union.anon = type { %struct.GAP }
%union.rec = type { %struct.head_type }
@zz_hold = external global %union.rec* ; <%union.rec**> [#uses=2]
@zz_res = external global %union.rec* ; <%union.rec**> [#uses=1]
define %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind {
entry:
; CHECK: ldr{{(.w)?}} {{(r[0-9]+)|(lr)}}, [r7, #28]
%xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
%ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
br label %bb20
bb20: ; preds = %entry
switch i32 undef, label %bb1287 [
i32 11, label %bb119
i32 12, label %bb119
i32 21, label %bb420
i32 23, label %bb420
i32 45, label %bb438
i32 46, label %bb438
i32 55, label %bb533
i32 56, label %bb569
i32 64, label %bb745
i32 78, label %bb1098
]
bb119: ; preds = %bb20, %bb20
unreachable
bb420: ; preds = %bb20, %bb20
; CHECK: bb420
; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp]
; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #4]
; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #8]
; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #24]
store %union.rec* null, %union.rec** @zz_hold, align 4
store %union.rec* null, %union.rec** @zz_res, align 4
store %union.rec* %x, %union.rec** @zz_hold, align 4
%0 = call %union.rec* @Manifest(%union.rec* undef, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind ; <%union.rec*> [#uses=0]
unreachable
bb438: ; preds = %bb20, %bb20
unreachable
bb533: ; preds = %bb20
ret %union.rec* %x
bb569: ; preds = %bb20
unreachable
bb745: ; preds = %bb20
unreachable
bb1098: ; preds = %bb20
unreachable
bb1287: ; preds = %bb20
unreachable
}