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https://github.com/c64scene-ar/llvm-6502.git
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aed12d4bad
Disable the SGPR usage restriction parts of the DAG legalizeOperands. It now should only be doing immediate folding until it can be replaced later. The real legalization work is now done by the other SIInstrInfo::legalizeOperands git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218531 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
2.0 KiB
LLVM
69 lines
2.0 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
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; FUNC-LABEL: @fneg_f32
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; R600: -PV
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; SI: V_XOR_B32
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define void @fneg_f32(float addrspace(1)* %out, float %in) {
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%fneg = fsub float -0.000000e+00, %in
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store float %fneg, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fneg_v2f32
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; R600: -PV
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; R600: -PV
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; SI: V_XOR_B32
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; SI: V_XOR_B32
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define void @fneg_v2f32(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
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%fneg = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
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store <2 x float> %fneg, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fneg_v4f32
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; R600: -PV
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; R600: -T
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; R600: -PV
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; R600: -PV
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; SI: V_XOR_B32
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; SI: V_XOR_B32
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; SI: V_XOR_B32
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; SI: V_XOR_B32
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define void @fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
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%fneg = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
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store <4 x float> %fneg, <4 x float> addrspace(1)* %out
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ret void
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}
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; DAGCombiner will transform:
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; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000))
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; unless the target returns true for isNegFree()
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; FUNC-LABEL: @fneg_free_f32
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; R600-NOT: XOR
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; R600: -KC0[2].Z
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; XXX: We could use V_ADD_F32_e64 with the negate bit here instead.
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; SI: V_SUB_F32_e64 v{{[0-9]}}, 0.0, s{{[0-9]}}, 0, 0
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define void @fneg_free_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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%fsub = fsub float 0.0, %bc
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store float %fsub, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fneg_fold
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; SI: S_LOAD_DWORD [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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; SI-NOT: XOR
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; SI: V_MUL_F32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]]
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define void @fneg_fold_f32(float addrspace(1)* %out, float %in) {
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%fsub = fsub float -0.0, %in
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%fmul = fmul float %fsub, %in
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store float %fmul, float addrspace(1)* %out
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ret void
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}
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