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For some reason I never got around to adding these at the same time as the signed versions. No idea why. I'm not sure whether this SystemZII::BranchC* stuff is useful, or whether it should just be replaced with an "is normal" flag. I'll leave that for later though. There are some boundary conditions that can be tweaked, such as preferring unsigned comparisons for equality with [128, 256), and "<= 255" over "< 256", but again I'll leave those for a separate patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190930 91177308-0d34-0410-b5e6-96231b3b80d8
463 lines
16 KiB
C++
463 lines
16 KiB
C++
//===-- SystemZLongBranch.cpp - Branch lengthening for SystemZ ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass makes sure that all branches are in range. There are several ways
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// in which this could be done. One aggressive approach is to assume that all
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// branches are in range and successively replace those that turn out not
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// to be in range with a longer form (branch relaxation). A simple
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// implementation is to continually walk through the function relaxing
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// branches until no more changes are needed and a fixed point is reached.
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// However, in the pathological worst case, this implementation is
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// quadratic in the number of blocks; relaxing branch N can make branch N-1
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// go out of range, which in turn can make branch N-2 go out of range,
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// and so on.
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//
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// An alternative approach is to assume that all branches must be
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// converted to their long forms, then reinstate the short forms of
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// branches that, even under this pessimistic assumption, turn out to be
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// in range (branch shortening). This too can be implemented as a function
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// walk that is repeated until a fixed point is reached. In general,
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// the result of shortening is not as good as that of relaxation, and
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// shortening is also quadratic in the worst case; shortening branch N
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// can bring branch N-1 in range of the short form, which in turn can do
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// the same for branch N-2, and so on. The main advantage of shortening
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// is that each walk through the function produces valid code, so it is
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// possible to stop at any point after the first walk. The quadraticness
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// could therefore be handled with a maximum pass count, although the
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// question then becomes: what maximum count should be used?
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//
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// On SystemZ, long branches are only needed for functions bigger than 64k,
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// which are relatively rare to begin with, and the long branch sequences
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// are actually relatively cheap. It therefore doesn't seem worth spending
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// much compilation time on the problem. Instead, the approach we take is:
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//
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// (1) Work out the address that each block would have if no branches
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// need relaxing. Exit the pass early if all branches are in range
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// according to this assumption.
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//
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// (2) Work out the address that each block would have if all branches
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// need relaxing.
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//
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// (3) Walk through the block calculating the final address of each instruction
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// and relaxing those that need to be relaxed. For backward branches,
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// this check uses the final address of the target block, as calculated
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// earlier in the walk. For forward branches, this check uses the
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// address of the target block that was calculated in (2). Both checks
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// give a conservatively-correct range.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "systemz-long-branch"
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#include "SystemZTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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STATISTIC(LongBranches, "Number of long branches.");
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namespace {
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// Represents positional information about a basic block.
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struct MBBInfo {
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// The address that we currently assume the block has.
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uint64_t Address;
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// The size of the block in bytes, excluding terminators.
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// This value never changes.
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uint64_t Size;
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// The minimum alignment of the block, as a log2 value.
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// This value never changes.
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unsigned Alignment;
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// The number of terminators in this block. This value never changes.
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unsigned NumTerminators;
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MBBInfo()
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: Address(0), Size(0), Alignment(0), NumTerminators(0) {}
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};
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// Represents the state of a block terminator.
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struct TerminatorInfo {
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// If this terminator is a relaxable branch, this points to the branch
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// instruction, otherwise it is null.
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MachineInstr *Branch;
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// The address that we currently assume the terminator has.
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uint64_t Address;
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// The current size of the terminator in bytes.
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uint64_t Size;
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// If Branch is nonnull, this is the number of the target block,
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// otherwise it is unused.
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unsigned TargetBlock;
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// If Branch is nonnull, this is the length of the longest relaxed form,
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// otherwise it is zero.
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unsigned ExtraRelaxSize;
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TerminatorInfo() : Branch(0), Size(0), TargetBlock(0), ExtraRelaxSize(0) {}
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};
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// Used to keep track of the current position while iterating over the blocks.
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struct BlockPosition {
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// The address that we assume this position has.
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uint64_t Address;
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// The number of low bits in Address that are known to be the same
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// as the runtime address.
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unsigned KnownBits;
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BlockPosition(unsigned InitialAlignment)
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: Address(0), KnownBits(InitialAlignment) {}
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};
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class SystemZLongBranch : public MachineFunctionPass {
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public:
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static char ID;
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SystemZLongBranch(const SystemZTargetMachine &tm)
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: MachineFunctionPass(ID), TII(0) {}
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virtual const char *getPassName() const {
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return "SystemZ Long Branch";
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}
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bool runOnMachineFunction(MachineFunction &F);
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private:
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void skipNonTerminators(BlockPosition &Position, MBBInfo &Block);
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void skipTerminator(BlockPosition &Position, TerminatorInfo &Terminator,
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bool AssumeRelaxed);
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TerminatorInfo describeTerminator(MachineInstr *MI);
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uint64_t initMBBInfo();
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bool mustRelaxBranch(const TerminatorInfo &Terminator, uint64_t Address);
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bool mustRelaxABranch();
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void setWorstCaseAddresses();
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void splitBranchOnCount(MachineInstr *MI, unsigned AddOpcode);
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void splitCompareBranch(MachineInstr *MI, unsigned CompareOpcode);
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void relaxBranch(TerminatorInfo &Terminator);
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void relaxBranches();
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const SystemZInstrInfo *TII;
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MachineFunction *MF;
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SmallVector<MBBInfo, 16> MBBs;
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SmallVector<TerminatorInfo, 16> Terminators;
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};
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char SystemZLongBranch::ID = 0;
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const uint64_t MaxBackwardRange = 0x10000;
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const uint64_t MaxForwardRange = 0xfffe;
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} // end of anonymous namespace
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FunctionPass *llvm::createSystemZLongBranchPass(SystemZTargetMachine &TM) {
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return new SystemZLongBranch(TM);
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}
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// Position describes the state immediately before Block. Update Block
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// accordingly and move Position to the end of the block's non-terminator
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// instructions.
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void SystemZLongBranch::skipNonTerminators(BlockPosition &Position,
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MBBInfo &Block) {
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if (Block.Alignment > Position.KnownBits) {
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// When calculating the address of Block, we need to conservatively
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// assume that Block had the worst possible misalignment.
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Position.Address += ((uint64_t(1) << Block.Alignment) -
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(uint64_t(1) << Position.KnownBits));
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Position.KnownBits = Block.Alignment;
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}
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// Align the addresses.
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uint64_t AlignMask = (uint64_t(1) << Block.Alignment) - 1;
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Position.Address = (Position.Address + AlignMask) & ~AlignMask;
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// Record the block's position.
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Block.Address = Position.Address;
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// Move past the non-terminators in the block.
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Position.Address += Block.Size;
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}
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// Position describes the state immediately before Terminator.
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// Update Terminator accordingly and move Position past it.
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// Assume that Terminator will be relaxed if AssumeRelaxed.
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void SystemZLongBranch::skipTerminator(BlockPosition &Position,
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TerminatorInfo &Terminator,
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bool AssumeRelaxed) {
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Terminator.Address = Position.Address;
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Position.Address += Terminator.Size;
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if (AssumeRelaxed)
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Position.Address += Terminator.ExtraRelaxSize;
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}
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// Return a description of terminator instruction MI.
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TerminatorInfo SystemZLongBranch::describeTerminator(MachineInstr *MI) {
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TerminatorInfo Terminator;
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Terminator.Size = TII->getInstSizeInBytes(MI);
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if (MI->isConditionalBranch() || MI->isUnconditionalBranch()) {
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switch (MI->getOpcode()) {
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case SystemZ::J:
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// Relaxes to JG, which is 2 bytes longer.
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Terminator.ExtraRelaxSize = 2;
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break;
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case SystemZ::BRC:
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// Relaxes to BRCL, which is 2 bytes longer.
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Terminator.ExtraRelaxSize = 2;
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break;
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case SystemZ::BRCT:
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case SystemZ::BRCTG:
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// Relaxes to A(G)HI and BRCL, which is 6 bytes longer.
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Terminator.ExtraRelaxSize = 6;
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break;
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case SystemZ::CRJ:
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case SystemZ::CLRJ:
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// Relaxes to a C(L)R/BRCL sequence, which is 2 bytes longer.
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Terminator.ExtraRelaxSize = 2;
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break;
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case SystemZ::CGRJ:
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case SystemZ::CLGRJ:
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// Relaxes to a C(L)GR/BRCL sequence, which is 4 bytes longer.
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Terminator.ExtraRelaxSize = 4;
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break;
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case SystemZ::CIJ:
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case SystemZ::CGIJ:
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// Relaxes to a C(G)HI/BRCL sequence, which is 4 bytes longer.
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Terminator.ExtraRelaxSize = 4;
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break;
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case SystemZ::CLIJ:
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case SystemZ::CLGIJ:
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// Relaxes to a CL(G)FI/BRCL sequence, which is 6 bytes longer.
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Terminator.ExtraRelaxSize = 6;
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break;
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default:
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llvm_unreachable("Unrecognized branch instruction");
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}
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Terminator.Branch = MI;
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Terminator.TargetBlock =
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TII->getBranchInfo(MI).Target->getMBB()->getNumber();
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}
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return Terminator;
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}
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// Fill MBBs and Terminators, setting the addresses on the assumption
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// that no branches need relaxation. Return the size of the function under
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// this assumption.
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uint64_t SystemZLongBranch::initMBBInfo() {
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MF->RenumberBlocks();
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unsigned NumBlocks = MF->size();
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MBBs.clear();
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MBBs.resize(NumBlocks);
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Terminators.clear();
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Terminators.reserve(NumBlocks);
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BlockPosition Position(MF->getAlignment());
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for (unsigned I = 0; I < NumBlocks; ++I) {
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MachineBasicBlock *MBB = MF->getBlockNumbered(I);
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MBBInfo &Block = MBBs[I];
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// Record the alignment, for quick access.
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Block.Alignment = MBB->getAlignment();
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// Calculate the size of the fixed part of the block.
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MachineBasicBlock::iterator MI = MBB->begin();
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MachineBasicBlock::iterator End = MBB->end();
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while (MI != End && !MI->isTerminator()) {
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Block.Size += TII->getInstSizeInBytes(MI);
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++MI;
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}
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skipNonTerminators(Position, Block);
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// Add the terminators.
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while (MI != End) {
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if (!MI->isDebugValue()) {
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assert(MI->isTerminator() && "Terminator followed by non-terminator");
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Terminators.push_back(describeTerminator(MI));
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skipTerminator(Position, Terminators.back(), false);
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++Block.NumTerminators;
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}
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++MI;
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}
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}
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return Position.Address;
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}
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// Return true if, under current assumptions, Terminator would need to be
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// relaxed if it were placed at address Address.
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bool SystemZLongBranch::mustRelaxBranch(const TerminatorInfo &Terminator,
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uint64_t Address) {
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if (!Terminator.Branch)
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return false;
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const MBBInfo &Target = MBBs[Terminator.TargetBlock];
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if (Address >= Target.Address) {
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if (Address - Target.Address <= MaxBackwardRange)
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return false;
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} else {
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if (Target.Address - Address <= MaxForwardRange)
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return false;
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}
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return true;
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}
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// Return true if, under current assumptions, any terminator needs
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// to be relaxed.
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bool SystemZLongBranch::mustRelaxABranch() {
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for (SmallVectorImpl<TerminatorInfo>::iterator TI = Terminators.begin(),
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TE = Terminators.end(); TI != TE; ++TI)
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if (mustRelaxBranch(*TI, TI->Address))
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return true;
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return false;
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}
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// Set the address of each block on the assumption that all branches
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// must be long.
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void SystemZLongBranch::setWorstCaseAddresses() {
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SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
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BlockPosition Position(MF->getAlignment());
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for (SmallVectorImpl<MBBInfo>::iterator BI = MBBs.begin(), BE = MBBs.end();
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BI != BE; ++BI) {
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skipNonTerminators(Position, *BI);
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for (unsigned BTI = 0, BTE = BI->NumTerminators; BTI != BTE; ++BTI) {
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skipTerminator(Position, *TI, true);
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++TI;
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}
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}
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}
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// Split BRANCH ON COUNT MI into the addition given by AddOpcode followed
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// by a BRCL on the result.
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void SystemZLongBranch::splitBranchOnCount(MachineInstr *MI,
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unsigned AddOpcode) {
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MachineBasicBlock *MBB = MI->getParent();
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DebugLoc DL = MI->getDebugLoc();
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BuildMI(*MBB, MI, DL, TII->get(AddOpcode))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(1))
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.addImm(-1);
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MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
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.addImm(SystemZ::CCMASK_ICMP)
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.addImm(SystemZ::CCMASK_CMP_NE)
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.addOperand(MI->getOperand(2));
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// The implicit use of CC is a killing use.
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BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo());
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MI->eraseFromParent();
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}
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// Split MI into the comparison given by CompareOpcode followed
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// a BRCL on the result.
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void SystemZLongBranch::splitCompareBranch(MachineInstr *MI,
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unsigned CompareOpcode) {
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MachineBasicBlock *MBB = MI->getParent();
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DebugLoc DL = MI->getDebugLoc();
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BuildMI(*MBB, MI, DL, TII->get(CompareOpcode))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(1));
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MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
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.addImm(SystemZ::CCMASK_ICMP)
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.addOperand(MI->getOperand(2))
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.addOperand(MI->getOperand(3));
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// The implicit use of CC is a killing use.
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BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo());
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MI->eraseFromParent();
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}
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// Relax the branch described by Terminator.
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void SystemZLongBranch::relaxBranch(TerminatorInfo &Terminator) {
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MachineInstr *Branch = Terminator.Branch;
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switch (Branch->getOpcode()) {
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case SystemZ::J:
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Branch->setDesc(TII->get(SystemZ::JG));
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break;
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case SystemZ::BRC:
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Branch->setDesc(TII->get(SystemZ::BRCL));
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break;
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case SystemZ::BRCT:
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splitBranchOnCount(Branch, SystemZ::AHI);
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break;
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case SystemZ::BRCTG:
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splitBranchOnCount(Branch, SystemZ::AGHI);
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break;
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case SystemZ::CRJ:
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splitCompareBranch(Branch, SystemZ::CR);
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break;
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case SystemZ::CGRJ:
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splitCompareBranch(Branch, SystemZ::CGR);
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break;
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case SystemZ::CIJ:
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splitCompareBranch(Branch, SystemZ::CHI);
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break;
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case SystemZ::CGIJ:
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splitCompareBranch(Branch, SystemZ::CGHI);
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break;
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case SystemZ::CLRJ:
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splitCompareBranch(Branch, SystemZ::CLR);
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break;
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case SystemZ::CLGRJ:
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splitCompareBranch(Branch, SystemZ::CLGR);
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break;
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case SystemZ::CLIJ:
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splitCompareBranch(Branch, SystemZ::CLFI);
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break;
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case SystemZ::CLGIJ:
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splitCompareBranch(Branch, SystemZ::CLGFI);
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break;
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default:
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llvm_unreachable("Unrecognized branch");
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}
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Terminator.Size += Terminator.ExtraRelaxSize;
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Terminator.ExtraRelaxSize = 0;
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Terminator.Branch = 0;
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++LongBranches;
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}
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// Run a shortening pass and relax any branches that need to be relaxed.
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void SystemZLongBranch::relaxBranches() {
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SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
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BlockPosition Position(MF->getAlignment());
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for (SmallVectorImpl<MBBInfo>::iterator BI = MBBs.begin(), BE = MBBs.end();
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BI != BE; ++BI) {
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skipNonTerminators(Position, *BI);
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for (unsigned BTI = 0, BTE = BI->NumTerminators; BTI != BTE; ++BTI) {
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assert(Position.Address <= TI->Address &&
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"Addresses shouldn't go forwards");
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if (mustRelaxBranch(*TI, Position.Address))
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relaxBranch(*TI);
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skipTerminator(Position, *TI, false);
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++TI;
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}
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}
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}
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bool SystemZLongBranch::runOnMachineFunction(MachineFunction &F) {
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TII = static_cast<const SystemZInstrInfo *>(F.getTarget().getInstrInfo());
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MF = &F;
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uint64_t Size = initMBBInfo();
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if (Size <= MaxForwardRange || !mustRelaxABranch())
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return false;
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setWorstCaseAddresses();
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relaxBranches();
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return true;
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}
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