mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-20 11:29:24 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41627 91177308-0d34-0410-b5e6-96231b3b80d8
654 lines
22 KiB
C++
654 lines
22 KiB
C++
//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the Raul Herbster and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the pass that transforms the ARM machine instructions into
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// relocatable machine code.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-emitter"
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#include "ARMInstrInfo.h"
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#include "ARMSubtarget.h"
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#include "ARMTargetMachine.h"
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#include "ARMRelocations.h"
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#include "ARMAddressingModes.h"
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#include "ARM.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Compiler.h"
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using namespace llvm;
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STATISTIC(NumEmitted, "Number of machine instructions emitted");
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namespace {
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class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
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const ARMInstrInfo *II;
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const TargetData *TD;
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TargetMachine &TM;
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MachineCodeEmitter &MCE;
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public:
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static char ID;
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explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
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: MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm),
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MCE(mce) {}
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Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
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const ARMInstrInfo &ii, const TargetData &td)
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: MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm),
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MCE(mce) {}
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bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "ARM Machine Code Emitter";
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}
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void emitInstruction(const MachineInstr &MI);
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int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);
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unsigned getBaseOpcodeFor(const TargetInstrDescriptor *TID);
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unsigned getBinaryCodeForInstr(const MachineInstr &MI);
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void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
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void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
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void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
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int Disp = 0, unsigned PCAdj = 0 );
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void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
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unsigned PCAdj = 0);
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void emitGlobalConstant(const Constant *CV);
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void emitMachineBasicBlock(MachineBasicBlock *BB);
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private:
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int getShiftOp(const MachineOperand &MO);
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};
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char Emitter::ID = 0;
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}
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/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
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/// to the specified MCE object.
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FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
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MachineCodeEmitter &MCE) {
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return new Emitter(TM, MCE);
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}
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bool Emitter::runOnMachineFunction(MachineFunction &MF) {
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assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
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MF.getTarget().getRelocationModel() != Reloc::Static) &&
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"JIT relocation model must be set to static or default!");
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II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
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TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
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do {
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MCE.startFunction(MF);
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for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
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MBB != E; ++MBB) {
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MCE.StartMachineBasicBlock(MBB);
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for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I)
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emitInstruction(*I);
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}
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} while (MCE.finishFunction(MF));
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return false;
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}
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/// getBaseOpcodeFor - Return the opcode value
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unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) {
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return (TID->TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
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}
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/// getShiftOp - Verify which is the shift opcode (bit[6:5]) of the
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/// machine operand.
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int Emitter::getShiftOp(const MachineOperand &MO) {
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unsigned ShiftOp = 0x0;
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switch(ARM_AM::getAM2ShiftOpc(MO.getImmedValue())) {
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default: assert(0 && "Unknown shift opc!");
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case ARM_AM::asr:
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ShiftOp = 0X2;
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break;
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case ARM_AM::lsl:
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ShiftOp = 0X0;
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break;
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case ARM_AM::lsr:
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ShiftOp = 0X1;
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break;
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case ARM_AM::ror:
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case ARM_AM::rrx:
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ShiftOp = 0X3;
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break;
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}
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return ShiftOp;
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}
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int Emitter::getMachineOpValue(const MachineInstr &MI, unsigned OpIndex) {
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intptr_t rv = 0;
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const MachineOperand &MO = MI.getOperand(OpIndex);
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if (MO.isRegister()) {
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assert(MRegisterInfo::isPhysicalRegister(MO.getReg()));
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rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
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} else if (MO.isImmediate()) {
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rv = MO.getImmedValue();
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} else if (MO.isGlobalAddress()) {
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emitGlobalAddressForCall(MO.getGlobal(), false);
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} else if (MO.isExternalSymbol()) {
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emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
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} else if (MO.isConstantPoolIndex()) {
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emitConstPoolAddress(MO.getConstantPoolIndex(), ARM::reloc_arm_relative);
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} else if (MO.isJumpTableIndex()) {
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emitJumpTableAddress(MO.getJumpTableIndex(), ARM::reloc_arm_relative);
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} else if (MO.isMachineBasicBlock()) {
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emitMachineBasicBlock(MO.getMachineBasicBlock());
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}
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return rv;
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}
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/// emitGlobalAddressForCall - Emit the specified address to the code stream
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/// assuming this is part of a function call, which is PC relative.
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///
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void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) {
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MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
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ARM::reloc_arm_branch, GV, 0,
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DoesntNeedStub));
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}
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/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
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/// be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
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MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
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Reloc, ES));
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}
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/// emitConstPoolAddress - Arrange for the address of an constant pool
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/// to be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
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int Disp /* = 0 */,
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unsigned PCAdj /* = 0 */) {
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MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
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Reloc, CPI, PCAdj));
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}
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/// emitJumpTableAddress - Arrange for the address of a jump table to
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/// be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
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unsigned PCAdj /* = 0 */) {
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MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
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Reloc, JTI, PCAdj));
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}
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/// emitMachineBasicBlock - Emit the specified address basic block.
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void Emitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
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MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
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ARM::reloc_arm_branch, BB));
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}
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void Emitter::emitInstruction(const MachineInstr &MI) {
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NumEmitted++; // Keep track of the # of mi's emitted
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MCE.emitWordLE(getBinaryCodeForInstr(MI));
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}
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unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
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const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
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const unsigned opcode = MI.getOpcode();
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// initial instruction mask
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unsigned Value = 0xE0000000;
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unsigned op;
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switch (Desc->TSFlags & ARMII::AddrModeMask) {
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case ARMII::AddrModeNone: {
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switch(Desc->TSFlags & ARMII::FormMask) {
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default: {
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assert(0 && "Unknown instruction subtype!");
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// treat special instruction CLZ
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if(opcode == ARM::CLZ) {
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// set first operand
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op = getMachineOpValue(MI,0);
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Value |= op << ARMII::RegRdShift;
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// set second operand
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op = getMachineOpValue(MI,1);
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Value |= op;
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}
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break;
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}
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case ARMII::MulSMLAW:
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case ARMII::MulSMULW:
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// set bit W(21)
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Value |= 1 << 21;
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case ARMII::MulSMLA:
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case ARMII::MulSMUL: {
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// set bit W(21)
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Value |= 1 << 24;
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// set opcode (bit[7:4]). For more information, see ARM-ARM page A3-31
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// SMLA<x><y> - 1yx0
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// SMLAW<y> - 1y00
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// SMULW<y> - 1y10
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// SMUL<x><y> - 1yx0
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unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
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Value |= BaseOpcode << 4;
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unsigned Format = (Desc->TSFlags & ARMII::FormMask);
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if (Format == ARMII::MulSMUL)
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Value |= 1 << 22;
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// set first operand
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op = getMachineOpValue(MI,0);
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Value |= op << ARMII::RegRnShift;
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// set second operand
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op = getMachineOpValue(MI,1);
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Value |= op;
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// set third operand
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op = getMachineOpValue(MI,2);
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Value |= op << ARMII::RegRsShift;
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// instructions SMLA and SMLAW have a fourth operand
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if (Format != ARMII::MulSMULW && Format != ARMII::MulSMUL) {
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op = getMachineOpValue(MI,3);
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Value |= op << ARMII::RegRdShift;
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}
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break;
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}
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case ARMII::MulFrm: {
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// bit[7:4] is always 9
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Value |= 9 << 4;
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// set opcode (bit[23:20])
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unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
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Value |= BaseOpcode << 20;
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bool isMUL = opcode == ARM::MUL;
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bool isMLA = opcode == ARM::MLA;
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// set first operand
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op = getMachineOpValue(MI,0);
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Value |= op << (isMUL || isMLA ? ARMII::RegRnShift : ARMII::RegRdShift);
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// set second operand
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op = getMachineOpValue(MI,1);
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Value |= op << (isMUL || isMLA ? 0 : ARMII::RegRnShift);
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// set third operand
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op = getMachineOpValue(MI,2);
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Value |= op << (isMUL || isMLA ? ARMII::RegRsShift : 0);
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// multiply instructions (except MUL), have a fourth operand
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if (!isMUL) {
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op = getMachineOpValue(MI,3);
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Value |= op << (isMLA ? ARMII::RegRdShift : ARMII::RegRsShift);
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}
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break;
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}
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case ARMII::Branch: {
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// set opcode (bit[27:24])
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unsigned BaseOpcode = getBaseOpcodeFor(Desc);
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Value |= BaseOpcode << 24;
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// set signed_immed_24 field
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op = getMachineOpValue(MI,0);
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Value |= op;
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// if it is a conditional branch, set cond field
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if (opcode == ARM::Bcc) {
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op = getMachineOpValue(MI,1);
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Value &= 0x0FFFFFFF; // clear conditional field
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Value |= op << 28; // set conditional field
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}
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break;
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}
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case ARMII::BranchMisc: {
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// set opcode (bit[7:4])
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unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
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Value |= BaseOpcode << 4;
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// set bit[27:24] to 1, set bit[23:20] to 2 and set bit[19:8] to 0xFFF
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Value |= 0x12fff << 8;
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if (opcode == ARM::BX_RET)
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op = 0xe; // the return register is LR
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else
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// otherwise, set the return register
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op = getMachineOpValue(MI,0);
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Value |= op;
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break;
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}
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case ARMII::Pseudo:
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break;
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}
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break;
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}
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case ARMII::AddrMode1: {
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// set opcode (bit[24:21]) of data-processing instructions
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unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
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Value |= BaseOpcode << 21;
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// treat 3 special instructions: MOVsra_flag, MOVsrl_flag and
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// MOVrx.
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unsigned Format = (Desc->TSFlags & ARMII::FormMask);
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if (Format == ARMII::DPRdMisc) {
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Value |= getMachineOpValue(MI,0) << ARMII::RegRdShift;
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Value |= getMachineOpValue(MI,1);
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switch(opcode) {
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case ARM::MOVsra_flag: {
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Value |= 0x1 << 6;
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Value |= 0x1 << 7;
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break;
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}
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case ARM::MOVsrl_flag: {
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Value |= 0x1 << 5;
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Value |= 0x1 << 7;
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break;
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}
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case ARM::MOVrx: {
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Value |= 0x3 << 5;
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break;
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}
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}
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break;
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}
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// Data processing operand instructions has 3 possible encodings (for more
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// information, see ARM-ARM page A3-10):
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// 1. <instr> <Rd>,<shifter_operand>
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// 2. <instr> <Rn>,<shifter_operand>
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// 3. <instr> <Rd>,<Rn>,<shifter_operand>
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bool IsDataProcessing1 = Format == ARMII::DPRdIm ||
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Format == ARMII::DPRdReg ||
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Format == ARMII::DPRdSoReg;
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bool IsDataProcessing2 = Format == ARMII::DPRnIm ||
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Format == ARMII::DPRnReg ||
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Format == ARMII::DPRnSoReg;
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bool IsDataProcessing3 = false;
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// set bit S(20)
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if (Format == ARMII::DPRImS || Format == ARMII::DPRRegS ||
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Format == ARMII::DPRSoRegS || IsDataProcessing2) {
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Value |= 1 << ARMII::S_BitShift;
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IsDataProcessing3 = !IsDataProcessing2;
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}
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IsDataProcessing3 = Format == ARMII::DPRIm ||
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Format == ARMII::DPRReg ||
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Format == ARMII::DPRSoReg ||
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IsDataProcessing3;
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// set first operand
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op = getMachineOpValue(MI,0);
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if (IsDataProcessing1 || IsDataProcessing3) {
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Value |= op << ARMII::RegRdShift;
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} else if (IsDataProcessing2) {
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Value |= op << ARMII::RegRnShift;
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}
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// set second operand of data processing #3 instructions
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if (IsDataProcessing3) {
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op = getMachineOpValue(MI,1);
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Value |= op << ARMII::RegRnShift;
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}
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unsigned OperandIndex = IsDataProcessing3 ? 2 : 1;
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switch (Format) {
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case ARMII::DPRdIm: case ARMII::DPRnIm:
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case ARMII::DPRIm: case ARMII::DPRImS: {
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// set bit I(25) to identify this is the immediate form of <shifter_op>
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Value |= 1 << ARMII::I_BitShift;
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// set immed_8 field
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const MachineOperand &MO = MI.getOperand(OperandIndex);
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op = ARM_AM::getSOImmVal(MO.getImmedValue());
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Value |= op;
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break;
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}
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case ARMII::DPRdReg: case ARMII::DPRnReg:
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case ARMII::DPRReg: case ARMII::DPRRegS: {
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// set last operand (register Rm)
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op = getMachineOpValue(MI,OperandIndex);
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Value |= op;
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break;
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}
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case ARMII::DPRdSoReg: case ARMII::DPRnSoReg:
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case ARMII::DPRSoReg: case ARMII::DPRSoRegS: {
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// set last operand (register Rm)
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op = getMachineOpValue(MI,OperandIndex);
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Value |= op;
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const MachineOperand &MO1 = MI.getOperand(OperandIndex + 1);
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const MachineOperand &MO2 = MI.getOperand(OperandIndex + 2);
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// identify it the instr is in immed or register shifts encoding
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bool IsShiftByRegister = MO1.getReg() > 0;
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// set shift operand (bit[6:4]).
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// ASR - 101 if it is in register shifts encoding; 100, otherwise.
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// LSL - 001 if it is in register shifts encoding; 000, otherwise.
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// LSR - 011 if it is in register shifts encoding; 010, otherwise.
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// ROR - 111 if it is in register shifts encoding; 110, otherwise.
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// RRX - 110 and bit[11:7] clear.
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switch(ARM_AM::getSORegShOp(MO2.getImmedValue())) {
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default: assert(0 && "Unknown shift opc!");
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case ARM_AM::asr: {
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if(IsShiftByRegister)
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Value |= 0x5 << 4;
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else
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Value |= 0x1 << 6;
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break;
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}
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case ARM_AM::lsl: {
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if(IsShiftByRegister)
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Value |= 0x1 << 4;
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break;
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}
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case ARM_AM::lsr: {
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if(IsShiftByRegister)
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Value |= 0x3 << 4;
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else
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Value |= 0x1 << 5;
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break;
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}
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case ARM_AM::ror: {
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if(IsShiftByRegister)
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Value |= 0x7 << 4;
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else
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Value |= 0x3 << 5;
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break;
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}
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case ARM_AM::rrx: {
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Value |= 0x3 << 5;
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break;
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}
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}
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// set the field related to shift operations (except rrx).
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if(ARM_AM::getSORegShOp(MO2.getImmedValue()) != ARM_AM::rrx)
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if(IsShiftByRegister) {
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// set the value of bit[11:8] (register Rs).
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assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
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op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg());
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assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
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Value |= op << ARMII::RegRsShift;
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} else {
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// set the value of bit [11:7] (shift_immed field).
|
|
op = ARM_AM::getSORegOffset(MO2.getImm());
|
|
Value |= op << 7;
|
|
}
|
|
break;
|
|
}
|
|
default: assert(false && "Unknown operand type!");
|
|
break;
|
|
}
|
|
|
|
break;
|
|
}
|
|
case ARMII::AddrMode2: {
|
|
// bit 26 is always 1
|
|
Value |= 1 << 26;
|
|
|
|
unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
|
|
// if the instruction uses offset addressing or pre-indexed addressing,
|
|
// set bit P(24) to 1
|
|
if (Index == ARMII::IndexModePre || Index == 0)
|
|
Value |= 1 << ARMII::IndexShift;
|
|
// if the instruction uses post-indexed addressing, set bit W(21) to 1
|
|
if (Index == ARMII::IndexModePre)
|
|
Value |= 1 << 21;
|
|
|
|
unsigned Format = (Desc->TSFlags & ARMII::FormMask);
|
|
// If it is a load instruction (except LDRD), set bit L(20) to 1
|
|
if (Format == ARMII::LdFrm)
|
|
Value |= 1 << ARMII::L_BitShift;
|
|
|
|
// set bit B(22)
|
|
unsigned BitByte = getBaseOpcodeFor(Desc);
|
|
Value |= BitByte << 22;
|
|
|
|
// set first operand
|
|
op = getMachineOpValue(MI,0);
|
|
Value |= op << ARMII::RegRdShift;
|
|
|
|
// set second operand
|
|
op = getMachineOpValue(MI,1);
|
|
Value |= op << ARMII::RegRnShift;
|
|
|
|
const MachineOperand &MO2 = MI.getOperand(2);
|
|
const MachineOperand &MO3 = MI.getOperand(3);
|
|
|
|
// set bit U(23) according to signal of immed value (positive or negative)
|
|
Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
|
|
ARMII::U_BitShift;
|
|
if (!MO2.getReg()) { // is immediate
|
|
if (ARM_AM::getAM2Offset(MO3.getImm()))
|
|
// set the value of offset_12 field
|
|
Value |= ARM_AM::getAM2Offset(MO3.getImm());
|
|
break;
|
|
}
|
|
|
|
// set bit I(25), because this is not in immediate enconding.
|
|
Value |= 1 << ARMII::I_BitShift;
|
|
assert(MRegisterInfo::isPhysicalRegister(MO2.getReg()));
|
|
// set bit[3:0] to the corresponding Rm register
|
|
Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
|
|
|
|
// if this instr is in scaled register offset/index instruction, set
|
|
// shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
|
|
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
|
|
unsigned ShiftOp = getShiftOp(MO3);
|
|
Value |= ShiftOp << 5; // shift
|
|
Value |= ShImm << 7; // shift_immed
|
|
}
|
|
|
|
break;
|
|
}
|
|
case ARMII::AddrMode3: {
|
|
|
|
unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
|
|
// if the instruction uses offset addressing or pre-indexed addressing,
|
|
// set bit P(24) to 1
|
|
if (Index == ARMII::IndexModePre || Index == 0)
|
|
Value |= 1 << ARMII::IndexShift;
|
|
|
|
unsigned Format = (Desc->TSFlags & ARMII::FormMask);
|
|
// If it is a load instruction (except LDRD), set bit L(20) to 1
|
|
if (Format == ARMII::LdFrm && opcode != ARM::LDRD)
|
|
Value |= 1 << ARMII::L_BitShift;
|
|
|
|
// bit[7:4] is the opcode of this instruction class (bits S and H).
|
|
unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
|
|
Value |= BaseOpcode << 4;
|
|
|
|
// set first operand
|
|
op = getMachineOpValue(MI,0);
|
|
Value |= op << ARMII::RegRdShift;
|
|
|
|
// set second operand
|
|
op = getMachineOpValue(MI,1);
|
|
Value |= op << ARMII::RegRnShift;
|
|
|
|
const MachineOperand &MO2 = MI.getOperand(2);
|
|
const MachineOperand &MO3 = MI.getOperand(3);
|
|
|
|
// set bit U(23) according to signal of immed value (positive or negative)
|
|
Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
|
|
ARMII::U_BitShift;
|
|
|
|
// if this instr is in register offset/index encoding, set bit[3:0]
|
|
// to the corresponding Rm register.
|
|
if (MO2.getReg()) {
|
|
Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
|
|
break;
|
|
}
|
|
|
|
// if this instr is in immediate offset/index encoding, set bit 22 to 1
|
|
if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
|
|
Value |= 1 << 22;
|
|
// set operands
|
|
Value |= (ImmOffs >> 4) << 8; // immedH
|
|
Value |= (ImmOffs & ~0xF); // immedL
|
|
}
|
|
|
|
break;
|
|
}
|
|
case ARMII::AddrMode4: {
|
|
// bit 27 is always 1
|
|
Value |= 1 << 27;
|
|
|
|
unsigned Format = (Desc->TSFlags & ARMII::FormMask);
|
|
// if it is a load instr, set bit L(20) to 1
|
|
if (Format == ARMII::LdFrm)
|
|
Value |= 1 << ARMII::L_BitShift;
|
|
|
|
unsigned OpIndex = 0;
|
|
|
|
// set first operand
|
|
op = getMachineOpValue(MI,OpIndex);
|
|
Value |= op << ARMII::RegRnShift;
|
|
|
|
// set addressing mode by modifying bits U(23) and P(24)
|
|
// IA - Increment after - bit U = 1 and bit P = 0
|
|
// IB - Increment before - bit U = 1 and bit P = 1
|
|
// DA - Decrement after - bit U = 0 and bit P = 0
|
|
// DB - Decrement before - bit U = 0 and bit P = 1
|
|
const MachineOperand &MO = MI.getOperand(OpIndex + 1);
|
|
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
|
|
switch(Mode) {
|
|
default: assert(0 && "Unknown addressing sub-mode!");
|
|
case ARM_AM::ia: Value |= 0x1 << 23; break;
|
|
case ARM_AM::ib: Value |= 0x3 << 23; break;
|
|
case ARM_AM::da: break;
|
|
case ARM_AM::db: Value |= 0x1 << 24; break;
|
|
}
|
|
|
|
// set bit W(21)
|
|
if (ARM_AM::getAM4WBFlag(MO.getImm()))
|
|
Value |= 0x1 << 21;
|
|
|
|
// set registers
|
|
for (unsigned i = OpIndex + 4, e = MI.getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MOR = MI.getOperand(i);
|
|
unsigned RegNumber = ARMRegisterInfo::getRegisterNumbering(MOR.getReg());
|
|
assert(MRegisterInfo::isPhysicalRegister(MOR.getReg()) && RegNumber < 16);
|
|
Value |= 0x1 << RegNumber;
|
|
}
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
return Value;
|
|
}
|