mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-04 16:01:46 +00:00
af0d72a6f9
Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211018 91177308-0d34-0410-b5e6-96231b3b80d8 |
||
|---|---|---|
| .. | ||
| CMakeLists.txt | ||
| LLVMBuild.txt | ||
| Makefile | ||
| MipsAsmBackend.cpp | ||
| MipsAsmBackend.h | ||
| MipsBaseInfo.h | ||
| MipsELFObjectWriter.cpp | ||
| MipsELFStreamer.cpp | ||
| MipsELFStreamer.h | ||
| MipsFixupKinds.h | ||
| MipsMCAsmInfo.cpp | ||
| MipsMCAsmInfo.h | ||
| MipsMCCodeEmitter.cpp | ||
| MipsMCCodeEmitter.h | ||
| MipsMCExpr.cpp | ||
| MipsMCExpr.h | ||
| MipsMCNaCl.h | ||
| MipsMCTargetDesc.cpp | ||
| MipsMCTargetDesc.h | ||
| MipsNaClELFStreamer.cpp | ||
| MipsTargetStreamer.cpp | ||