llvm-6502/test/MC/ARM/thumb_rewrites.s
Renato Golin 6215f78195 Elide repeated register operand in Thumb1 instructions
This patch makes the ARM backend transform 3 operand instructions such as
'adds/subs' to the 2 operand version of the same instruction if the first
two register operands are the same.

Example: 'adds r0, r0, #1' will is transformed to 'adds r0, #1'.

Currently for some instructions such as 'adds' if you try to assemble
'adds r0, r0, #8' for thumb v6m the assembler would throw an error message
because the immediate cannot be encoded using 3 bits.

The backend should be smart enough to transform the instruction to
'adds r0, #8', which allows for larger immediate constants.

Patch by Ranjeet Singh.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218521 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 16:14:29 +00:00

53 lines
1.5 KiB
ArmAsm

@ RUN: llvm-mc -triple thumbv6m -show-encoding < %s | FileCheck %s
adds r0, r0, #8
@ CHECK: adds r0, #8 @ encoding: [0x08,0x30]
adds r0, r0, r0
@ CHECK: adds r0, r0, r0 @ encoding: [0x00,0x18]
add r0, r0, r8
@ CHECK: add r0, r8 @ encoding: [0x40,0x44]
add sp, sp, r0
@ CHECK: add sp, r0 @ encoding: [0x85,0x44]
add r0, r0, r1
@ CHECK: add r0, r1 @ encoding: [0x08,0x44]
add r2, r2, r3
@ CHECK: add r2, r3 @ encoding: [0x1a,0x44]
subs r0, r0, r0
@ CHECK: subs r0, r0, r0 @ encoding: [0x00,0x1a]
ands r0, r0, r1
@ CHECK: ands r0, r1 @ encoding: [0x08,0x40]
eors r0, r0, r1
@ CHECK: eors r0, r1 @ encoding: [0x48,0x40]
lsls r0, r0, r1
@ CHECK: lsls r0, r1 @ encoding: [0x88,0x40]
lsrs r0, r0, r1
@ CHECK: lsrs r0, r1 @ encoding: [0xc8,0x40]
asrs r0, r0, r1
@ CHECK: asrs r0, r1 @ encoding: [0x08,0x41]
adcs r0, r0, r1
@ CHECK: adcs r0, r1 @ encoding: [0x48,0x41]
sbcs r0, r0, r1
@ CHECK: sbcs r0, r1 @ encoding: [0x88,0x41]
rors r0, r0, r1
@ CHECK: rors r0, r1 @ encoding: [0xc8,0x41]
orrs r0, r0, r1
@ CHECK: orrs r0, r1 @ encoding: [0x08,0x43]
bics r0, r0, r1
@ CHECK: bics r0, r1 @ encoding: [0x88,0x43]