mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
163 lines
5.2 KiB
LLVM
163 lines
5.2 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512bw -mattr=+avx512vl --show-mc-encoding| FileCheck %s
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; CHECK-LABEL: test_256_1
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; CHECK: vmovdqu8 {{.*}} ## encoding: [0x62
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; CHECK: ret
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define <32 x i8> @test_256_1(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <32 x i8>*
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%res = load <32 x i8>, <32 x i8>* %vaddr, align 1
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ret <32 x i8>%res
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}
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; CHECK-LABEL: test_256_2
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; CHECK: vmovdqu8{{.*}} ## encoding: [0x62
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; CHECK: ret
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define void @test_256_2(i8 * %addr, <32 x i8> %data) {
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%vaddr = bitcast i8* %addr to <32 x i8>*
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store <32 x i8>%data, <32 x i8>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test_256_3
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; CHECK: vmovdqu8{{.*{%k[1-7]} }}## encoding: [0x62
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; CHECK: ret
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define <32 x i8> @test_256_3(i8 * %addr, <32 x i8> %old, <32 x i8> %mask1) {
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%mask = icmp ne <32 x i8> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <32 x i8>*
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%r = load <32 x i8>, <32 x i8>* %vaddr, align 1
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%res = select <32 x i1> %mask, <32 x i8> %r, <32 x i8> %old
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ret <32 x i8>%res
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}
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; CHECK-LABEL: test_256_4
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; CHECK: vmovdqu8{{.*{%k[1-7]} {z} }}## encoding: [0x62
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; CHECK: ret
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define <32 x i8> @test_256_4(i8 * %addr, <32 x i8> %mask1) {
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%mask = icmp ne <32 x i8> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <32 x i8>*
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%r = load <32 x i8>, <32 x i8>* %vaddr, align 1
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%res = select <32 x i1> %mask, <32 x i8> %r, <32 x i8> zeroinitializer
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ret <32 x i8>%res
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}
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; CHECK-LABEL: test_256_5
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; CHECK: vmovdqu16{{.*}} ## encoding: [0x62
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; CHECK: ret
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define <16 x i16> @test_256_5(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <16 x i16>*
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%res = load <16 x i16>, <16 x i16>* %vaddr, align 1
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ret <16 x i16>%res
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}
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; CHECK-LABEL: test_256_6
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; CHECK: vmovdqu16{{.*}} ## encoding: [0x62
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; CHECK: ret
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define void @test_256_6(i8 * %addr, <16 x i16> %data) {
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%vaddr = bitcast i8* %addr to <16 x i16>*
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store <16 x i16>%data, <16 x i16>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test_256_7
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; CHECK: vmovdqu16{{.*{%k[1-7]} }}## encoding: [0x62
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; CHECK: ret
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define <16 x i16> @test_256_7(i8 * %addr, <16 x i16> %old, <16 x i16> %mask1) {
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%mask = icmp ne <16 x i16> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i16>*
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%r = load <16 x i16>, <16 x i16>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x i16> %r, <16 x i16> %old
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ret <16 x i16>%res
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}
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; CHECK-LABEL: test_256_8
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; CHECK: vmovdqu16{{.*{%k[1-7]} {z} }}## encoding: [0x62
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; CHECK: ret
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define <16 x i16> @test_256_8(i8 * %addr, <16 x i16> %mask1) {
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%mask = icmp ne <16 x i16> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i16>*
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%r = load <16 x i16>, <16 x i16>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x i16> %r, <16 x i16> zeroinitializer
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ret <16 x i16>%res
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}
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; CHECK-LABEL: test_128_1
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; CHECK: vmovdqu8 {{.*}} ## encoding: [0x62
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; CHECK: ret
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define <16 x i8> @test_128_1(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <16 x i8>*
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%res = load <16 x i8>, <16 x i8>* %vaddr, align 1
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ret <16 x i8>%res
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}
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; CHECK-LABEL: test_128_2
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; CHECK: vmovdqu8{{.*}} ## encoding: [0x62
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; CHECK: ret
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define void @test_128_2(i8 * %addr, <16 x i8> %data) {
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%vaddr = bitcast i8* %addr to <16 x i8>*
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store <16 x i8>%data, <16 x i8>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test_128_3
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; CHECK: vmovdqu8{{.*{%k[1-7]} }}## encoding: [0x62
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; CHECK: ret
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define <16 x i8> @test_128_3(i8 * %addr, <16 x i8> %old, <16 x i8> %mask1) {
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%mask = icmp ne <16 x i8> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i8>*
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%r = load <16 x i8>, <16 x i8>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x i8> %r, <16 x i8> %old
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ret <16 x i8>%res
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}
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; CHECK-LABEL: test_128_4
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; CHECK: vmovdqu8{{.*{%k[1-7]} {z} }}## encoding: [0x62
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; CHECK: ret
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define <16 x i8> @test_128_4(i8 * %addr, <16 x i8> %mask1) {
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%mask = icmp ne <16 x i8> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i8>*
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%r = load <16 x i8>, <16 x i8>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x i8> %r, <16 x i8> zeroinitializer
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ret <16 x i8>%res
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}
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; CHECK-LABEL: test_128_5
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; CHECK: vmovdqu16{{.*}} ## encoding: [0x62
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; CHECK: ret
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define <8 x i16> @test_128_5(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <8 x i16>*
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%res = load <8 x i16>, <8 x i16>* %vaddr, align 1
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ret <8 x i16>%res
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}
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; CHECK-LABEL: test_128_6
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; CHECK: vmovdqu16{{.*}} ## encoding: [0x62
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; CHECK: ret
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define void @test_128_6(i8 * %addr, <8 x i16> %data) {
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%vaddr = bitcast i8* %addr to <8 x i16>*
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store <8 x i16>%data, <8 x i16>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test_128_7
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; CHECK: vmovdqu16{{.*{%k[1-7]} }}## encoding: [0x62
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; CHECK: ret
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define <8 x i16> @test_128_7(i8 * %addr, <8 x i16> %old, <8 x i16> %mask1) {
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%mask = icmp ne <8 x i16> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i16>*
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%r = load <8 x i16>, <8 x i16>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x i16> %r, <8 x i16> %old
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ret <8 x i16>%res
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}
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; CHECK-LABEL: test_128_8
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; CHECK: vmovdqu16{{.*{%k[1-7]} {z} }}## encoding: [0x62
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; CHECK: ret
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define <8 x i16> @test_128_8(i8 * %addr, <8 x i16> %mask1) {
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%mask = icmp ne <8 x i16> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i16>*
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%r = load <8 x i16>, <8 x i16>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x i16> %r, <8 x i16> zeroinitializer
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ret <8 x i16>%res
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}
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