mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
341 lines
9.3 KiB
LLVM
341 lines
9.3 KiB
LLVM
; RUN: llc -O3 -mtriple=x86_64-unknown -mcpu=x86-64 -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE
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; RUN: llc -O3 -mtriple=x86_64-unknown -mcpu=x86-64 -mattr=+avx2 < %s | FileCheck %s --check-prefix=AVX
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;
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; Float Comparisons
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; Only equal/not-equal/ordered/unordered can be safely commuted
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;
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define <4 x i32> @commute_cmpps_eq(<4 x float>* %a0, <4 x float> %a1) #0 {
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;SSE-LABEL: commute_cmpps_eq
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;SSE: cmpeqps (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmpps_eq
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;AVX: vcmpeqps (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <4 x float>, <4 x float>* %a0
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%2 = fcmp oeq <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <4 x i32> @commute_cmpps_ne(<4 x float>* %a0, <4 x float> %a1) #0 {
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;SSE-LABEL: commute_cmpps_ne
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;SSE: cmpneqps (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmpps_ne
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;AVX: vcmpneqps (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <4 x float>, <4 x float>* %a0
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%2 = fcmp une <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <4 x i32> @commute_cmpps_ord(<4 x float>* %a0, <4 x float> %a1) #0 {
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;SSE-LABEL: commute_cmpps_ord
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;SSE: cmpordps (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmpps_ord
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;AVX: vcmpordps (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <4 x float>, <4 x float>* %a0
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%2 = fcmp ord <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <4 x i32> @commute_cmpps_uno(<4 x float>* %a0, <4 x float> %a1) #0 {
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;SSE-LABEL: commute_cmpps_uno
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;SSE: cmpunordps (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmpps_uno
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;AVX: vcmpunordps (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <4 x float>, <4 x float>* %a0
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%2 = fcmp uno <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <4 x i32> @commute_cmpps_lt(<4 x float>* %a0, <4 x float> %a1) #0 {
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;SSE-LABEL: commute_cmpps_lt
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;SSE: movaps (%rdi), %xmm1
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;SSE-NEXT: cmpltps %xmm0, %xmm1
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;SSE-NEXT: movaps %xmm1, %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmpps_lt
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;AVX: vmovaps (%rdi), %xmm1
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;AVX-NEXT: vcmpltps %xmm0, %xmm1, %xmm0
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;AVX-NEXT: retq
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%1 = load <4 x float>, <4 x float>* %a0
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%2 = fcmp olt <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <4 x i32> @commute_cmpps_le(<4 x float>* %a0, <4 x float> %a1) #0 {
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;SSE-LABEL: commute_cmpps_le
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;SSE: movaps (%rdi), %xmm1
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;SSE-NEXT: cmpleps %xmm0, %xmm1
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;SSE-NEXT: movaps %xmm1, %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmpps_le
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;AVX: vmovaps (%rdi), %xmm1
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;AVX-NEXT: vcmpleps %xmm0, %xmm1, %xmm0
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;AVX-NEXT: retq
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%1 = load <4 x float>, <4 x float>* %a0
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%2 = fcmp ole <4 x float> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <8 x i32> @commute_cmpps_eq_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
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;AVX-LABEL: commute_cmpps_eq_ymm
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;AVX: vcmpeqps (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <8 x float>, <8 x float>* %a0
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%2 = fcmp oeq <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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define <8 x i32> @commute_cmpps_ne_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
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;AVX-LABEL: commute_cmpps_ne_ymm
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;AVX: vcmpneqps (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <8 x float>, <8 x float>* %a0
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%2 = fcmp une <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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define <8 x i32> @commute_cmpps_ord_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
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;AVX-LABEL: commute_cmpps_ord_ymm
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;AVX: vcmpordps (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <8 x float>, <8 x float>* %a0
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%2 = fcmp ord <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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define <8 x i32> @commute_cmpps_uno_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
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;AVX-LABEL: commute_cmpps_uno_ymm
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;AVX: vcmpunordps (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <8 x float>, <8 x float>* %a0
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%2 = fcmp uno <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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define <8 x i32> @commute_cmpps_lt_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
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;AVX-LABEL: commute_cmpps_lt_ymm
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;AVX: vmovaps (%rdi), %ymm1
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;AVX-NEXT: vcmpltps %ymm0, %ymm1, %ymm0
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;AVX-NEXT: retq
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%1 = load <8 x float>, <8 x float>* %a0
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%2 = fcmp olt <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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define <8 x i32> @commute_cmpps_le_ymm(<8 x float>* %a0, <8 x float> %a1) #0 {
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;AVX-LABEL: commute_cmpps_le_ymm
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;AVX: vmovaps (%rdi), %ymm1
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;AVX-NEXT: vcmpleps %ymm0, %ymm1, %ymm0
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;AVX-NEXT: retq
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%1 = load <8 x float>, <8 x float>* %a0
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%2 = fcmp ole <8 x float> %1, %a1
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%3 = sext <8 x i1> %2 to <8 x i32>
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ret <8 x i32> %3
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}
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;
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; Double Comparisons
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; Only equal/not-equal/ordered/unordered can be safely commuted
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;
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define <2 x i64> @commute_cmppd_eq(<2 x double>* %a0, <2 x double> %a1) #0 {
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;SSE-LABEL: commute_cmppd_eq
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;SSE: cmpeqpd (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmppd_eq
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;AVX: vcmpeqpd (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <2 x double>, <2 x double>* %a0
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%2 = fcmp oeq <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @commute_cmppd_ne(<2 x double>* %a0, <2 x double> %a1) #0 {
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;SSE-LABEL: commute_cmppd_ne
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;SSE: cmpneqpd (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmppd_ne
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;AVX: vcmpneqpd (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <2 x double>, <2 x double>* %a0
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%2 = fcmp une <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @commute_cmppd_ord(<2 x double>* %a0, <2 x double> %a1) #0 {
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;SSE-LABEL: commute_cmppd_ord
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;SSE: cmpordpd (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmppd_ord
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;AVX: vcmpordpd (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <2 x double>, <2 x double>* %a0
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%2 = fcmp ord <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @commute_cmppd_uno(<2 x double>* %a0, <2 x double> %a1) #0 {
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;SSE-LABEL: commute_cmppd_uno
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;SSE: cmpunordpd (%rdi), %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmppd_uno
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;AVX: vcmpunordpd (%rdi), %xmm0, %xmm0
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;AVX-NEXT: retq
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%1 = load <2 x double>, <2 x double>* %a0
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%2 = fcmp uno <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @commute_cmppd_lt(<2 x double>* %a0, <2 x double> %a1) #0 {
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;SSE-LABEL: commute_cmppd_lt
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;SSE: movapd (%rdi), %xmm1
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;SSE-NEXT: cmpltpd %xmm0, %xmm1
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;SSE-NEXT: movapd %xmm1, %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmppd_lt
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;AVX: vmovapd (%rdi), %xmm1
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;AVX-NEXT: vcmpltpd %xmm0, %xmm1, %xmm0
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;AVX-NEXT: retq
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%1 = load <2 x double>, <2 x double>* %a0
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%2 = fcmp olt <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @commute_cmppd_le(<2 x double>* %a0, <2 x double> %a1) #0 {
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;SSE-LABEL: commute_cmppd_le
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;SSE: movapd (%rdi), %xmm1
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;SSE-NEXT: cmplepd %xmm0, %xmm1
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;SSE-NEXT: movapd %xmm1, %xmm0
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;SSE-NEXT: retq
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;AVX-LABEL: commute_cmppd_le
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;AVX: vmovapd (%rdi), %xmm1
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;AVX-NEXT: vcmplepd %xmm0, %xmm1, %xmm0
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;AVX-NEXT: retq
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%1 = load <2 x double>, <2 x double>* %a0
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%2 = fcmp ole <2 x double> %1, %a1
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%3 = sext <2 x i1> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <4 x i64> @commute_cmppd_eq_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
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;AVX-LABEL: commute_cmppd_eq
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;AVX: vcmpeqpd (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <4 x double>, <4 x double>* %a0
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%2 = fcmp oeq <4 x double> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i64>
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ret <4 x i64> %3
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}
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define <4 x i64> @commute_cmppd_ne_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
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;AVX-LABEL: commute_cmppd_ne
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;AVX: vcmpneqpd (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <4 x double>, <4 x double>* %a0
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%2 = fcmp une <4 x double> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i64>
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ret <4 x i64> %3
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}
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define <4 x i64> @commute_cmppd_ord_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
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;AVX-LABEL: commute_cmppd_ord
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;AVX: vcmpordpd (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <4 x double>, <4 x double>* %a0
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%2 = fcmp ord <4 x double> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i64>
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ret <4 x i64> %3
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}
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define <4 x i64> @commute_cmppd_uno_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
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;AVX-LABEL: commute_cmppd_uno
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;AVX: vcmpunordpd (%rdi), %ymm0, %ymm0
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;AVX-NEXT: retq
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%1 = load <4 x double>, <4 x double>* %a0
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%2 = fcmp uno <4 x double> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i64>
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ret <4 x i64> %3
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}
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define <4 x i64> @commute_cmppd_lt_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
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;AVX-LABEL: commute_cmppd_lt
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;AVX: vmovapd (%rdi), %ymm1
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;AVX-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
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;AVX-NEXT: retq
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%1 = load <4 x double>, <4 x double>* %a0
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%2 = fcmp olt <4 x double> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i64>
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ret <4 x i64> %3
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}
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define <4 x i64> @commute_cmppd_le_ymmm(<4 x double>* %a0, <4 x double> %a1) #0 {
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;AVX-LABEL: commute_cmppd_le
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;AVX: vmovapd (%rdi), %ymm1
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;AVX-NEXT: vcmplepd %ymm0, %ymm1, %ymm0
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;AVX-NEXT: retq
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%1 = load <4 x double>, <4 x double>* %a0
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%2 = fcmp ole <4 x double> %1, %a1
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%3 = sext <4 x i1> %2 to <4 x i64>
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ret <4 x i64> %3
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}
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