llvm-6502/test/CodeGen/X86/h-register-addressing-64.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

75 lines
2.0 KiB
LLVM

; RUN: llc < %s -march=x86-64 -mattr=-bmi | FileCheck %s
; Use h-register extract and zero-extend.
define double @foo8(double* nocapture inreg %p, i64 inreg %x) nounwind readonly {
%t0 = lshr i64 %x, 8
%t1 = and i64 %t0, 255
%t2 = getelementptr double, double* %p, i64 %t1
%t3 = load double, double* %t2, align 8
ret double %t3
}
; CHECK: foo8:
; CHECK: movzbl %{{[abcd]}}h, %e
define float @foo4(float* nocapture inreg %p, i64 inreg %x) nounwind readonly {
%t0 = lshr i64 %x, 8
%t1 = and i64 %t0, 255
%t2 = getelementptr float, float* %p, i64 %t1
%t3 = load float, float* %t2, align 8
ret float %t3
}
; CHECK: foo4:
; CHECK: movzbl %{{[abcd]}}h, %e
define i16 @foo2(i16* nocapture inreg %p, i64 inreg %x) nounwind readonly {
%t0 = lshr i64 %x, 8
%t1 = and i64 %t0, 255
%t2 = getelementptr i16, i16* %p, i64 %t1
%t3 = load i16, i16* %t2, align 8
ret i16 %t3
}
; CHECK: foo2:
; CHECK: movzbl %{{[abcd]}}h, %e
define i8 @foo1(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
%t0 = lshr i64 %x, 8
%t1 = and i64 %t0, 255
%t2 = getelementptr i8, i8* %p, i64 %t1
%t3 = load i8, i8* %t2, align 8
ret i8 %t3
}
; CHECK: foo1:
; CHECK: movzbl %{{[abcd]}}h, %e
define i8 @bar8(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
%t0 = lshr i64 %x, 5
%t1 = and i64 %t0, 2040
%t2 = getelementptr i8, i8* %p, i64 %t1
%t3 = load i8, i8* %t2, align 8
ret i8 %t3
}
; CHECK: bar8:
; CHECK: movzbl %{{[abcd]}}h, %e
define i8 @bar4(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
%t0 = lshr i64 %x, 6
%t1 = and i64 %t0, 1020
%t2 = getelementptr i8, i8* %p, i64 %t1
%t3 = load i8, i8* %t2, align 8
ret i8 %t3
}
; CHECK: bar4:
; CHECK: movzbl %{{[abcd]}}h, %e
define i8 @bar2(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
%t0 = lshr i64 %x, 7
%t1 = and i64 %t0, 510
%t2 = getelementptr i8, i8* %p, i64 %t1
%t3 = load i8, i8* %t2, align 8
ret i8 %t3
}
; CHECK: bar2:
; CHECK: movzbl %{{[abcd]}}h, %e
; CHECK: ret