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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
760 B
LLVM
27 lines
760 B
LLVM
; RUN: llc -march=x86 -mcpu=i486 -o - %s | FileCheck %s
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; Main test here was that ISelDAG could cope with a MachineNode in the chain
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; from the first load to the "X86ISD::SUB". Previously it thought that meant no
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; cycle could be formed so it tried to use "sub (%eax), [[RHS]]".
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define void @gst_atomic_queue_push(i32* %addr) {
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; CHECK-LABEL: gst_atomic_queue_push:
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; CHECK: movl (%eax), [[LHS:%e[a-z]+]]
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; CHECK: lock
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; CHECK-NEXT: orl
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; CHECK: movl (%eax), [[RHS:%e[a-z]+]]
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; CHECK: cmpl [[LHS]], [[RHS]]
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entry:
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br label %while.body
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while.body:
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%0 = load volatile i32, i32* %addr, align 4
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fence seq_cst
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%1 = load volatile i32, i32* %addr, align 4
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%cmp = icmp sgt i32 %1, %0
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br i1 %cmp, label %while.body, label %if.then
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if.then:
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ret void
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} |