mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
137 lines
2.6 KiB
LLVM
137 lines
2.6 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s
|
|
|
|
define <4 x i3> @test1(<4 x i3>* %in) nounwind {
|
|
%ret = load <4 x i3>, <4 x i3>* %in, align 1
|
|
ret <4 x i3> %ret
|
|
}
|
|
; CHECK-LABEL: test1
|
|
; CHECK: movzwl
|
|
; CHECK: shrl $3
|
|
; CHECK: andl $7
|
|
; CHECK: andl $7
|
|
; CHECK: vmovd
|
|
; CHECK: pinsrd $1
|
|
; CHECK: shrl $6
|
|
; CHECK: andl $7
|
|
; CHECK: pinsrd $2
|
|
; CHECK: shrl $9
|
|
; CHECK: andl $7
|
|
; CHECK: pinsrd $3
|
|
; CHECK: ret
|
|
|
|
define <4 x i1> @test2(<4 x i1>* %in) nounwind {
|
|
%ret = load <4 x i1>, <4 x i1>* %in, align 1
|
|
ret <4 x i1> %ret
|
|
}
|
|
|
|
; CHECK-LABEL: test2
|
|
; CHECK: movzbl
|
|
; CHECK: shrl
|
|
; CHECK: andl $1
|
|
; CHECK: andl $1
|
|
; CHECK: vmovd
|
|
; CHECK: pinsrd $1
|
|
; CHECK: shrl $2
|
|
; CHECK: andl $1
|
|
; CHECK: pinsrd $2
|
|
; CHECK: shrl $3
|
|
; CHECK: andl $1
|
|
; CHECK: pinsrd $3
|
|
; CHECK: ret
|
|
|
|
define <4 x i64> @test3(<4 x i1>* %in) nounwind {
|
|
%wide.load35 = load <4 x i1>, <4 x i1>* %in, align 1
|
|
%sext = sext <4 x i1> %wide.load35 to <4 x i64>
|
|
ret <4 x i64> %sext
|
|
}
|
|
|
|
; CHECK-LABEL: test3
|
|
; CHECK: movzbl
|
|
; CHECK: movq
|
|
; CHECK: shlq
|
|
; CHECK: sarq
|
|
; CHECK: vmovq
|
|
; CHECK: movq
|
|
; CHECK: shlq
|
|
; CHECK: sarq
|
|
; CHECK: vmovq
|
|
; CHECK: vpunpcklqdq
|
|
; CHECK: movq
|
|
; CHECK: shlq
|
|
; CHECK: sarq
|
|
; CHECK: vmovq
|
|
; CHECK: shlq
|
|
; CHECK: sarq
|
|
; CHECK: vmovq
|
|
; CHECK: vpunpcklqdq
|
|
; CHECK: vinsertf128
|
|
; CHECK: ret
|
|
|
|
define <16 x i4> @test4(<16 x i4>* %in) nounwind {
|
|
%ret = load <16 x i4>, <16 x i4>* %in, align 1
|
|
ret <16 x i4> %ret
|
|
}
|
|
|
|
; CHECK-LABEL: test4
|
|
; CHECK: movl
|
|
; CHECK-NEXT: shrl
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: movl
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: vmovd
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: movl
|
|
; CHECK-NEXT: shrl
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: movl
|
|
; CHECK-NEXT: shrl
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: movl
|
|
; CHECK-NEXT: shrl
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: movl
|
|
; CHECK-NEXT: shrl
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: movl
|
|
; CHECK-NEXT: shrl
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: movl
|
|
; CHECK-NEXT: shrl
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: movq
|
|
; CHECK-NEXT: shrq
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: movq
|
|
; CHECK-NEXT: shrq
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: movq
|
|
; CHECK-NEXT: shrq
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: movq
|
|
; CHECK-NEXT: shrq
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: movq
|
|
; CHECK-NEXT: shrq
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: movq
|
|
; CHECK-NEXT: shrq
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: movq
|
|
; CHECK-NEXT: shrq
|
|
; CHECK-NEXT: andl
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: shrq
|
|
; CHECK-NEXT: vpinsrb
|
|
; CHECK-NEXT: retq
|