mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
3957d4245f
This patch teaches the x86 backend how to efficiently lower ISD::BITCAST dag nodes from MVT::f64 to MVT::v4i16 (and vice versa), and from MVT::f64 to MVT::v8i8 (and vice versa). This patch extends the logic from revision 208107 to also handle MVT::v4i16 and MVT::v8i8. Also, this patch correctly propagates Undef values when performing the widening of a vector (example: when widening from v2i32 to v4i32, the upper 64bits of the resulting vector are 'undef'). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209451 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
850 B
LLVM
41 lines
850 B
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -mcpu=core2 -mattr=+mmx,+sse2 | FileCheck %s
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; rdar://6602459
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@g_v1di = external global <1 x i64>
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define void @t1() nounwind {
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entry:
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%call = call <1 x i64> @return_v1di() ; <<1 x i64>> [#uses=0]
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store <1 x i64> %call, <1 x i64>* @g_v1di
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ret void
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; CHECK-LABEL: t1:
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; CHECK: callq
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; CHECK-NEXT: movq _g_v1di
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; CHECK-NEXT: movq %rax,
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}
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declare <1 x i64> @return_v1di()
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define <1 x i64> @t2() nounwind {
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ret <1 x i64> <i64 1>
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; CHECK-LABEL: t2:
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; CHECK: movl $1
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; CHECK-NEXT: ret
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}
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define <2 x i32> @t3() nounwind {
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ret <2 x i32> <i32 1, i32 0>
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; CHECK-LABEL: t3:
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; CHECK: movl $1
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; CHECK: movd {{.*}}, %xmm0
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}
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define double @t4() nounwind {
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ret double bitcast (<2 x i32> <i32 1, i32 0> to double)
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; CHECK-LABEL: t4:
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; CHECK: movl $1
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; CHECK-NOT: pshufd
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; CHECK: movd {{.*}}, %xmm0
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}
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