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03a77831cc
Update the entire regression test suite for the new shuffles. Remove most of the old testing which was devoted to the old shuffle lowering path and is no longer relevant really. Also remove a few other random tests that only really exercised shuffles and only incidently or without any interesting aspects to them. Benchmarking that I have done shows a few small regressions with this on LNT, zero measurable regressions on real, large applications, and for several benchmarks where the loop vectorizer fires in the hot path it shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy Bridge machines. Running on AMD machines shows even more dramatic improvements. When using newer ISA vector extensions the gains are much more modest, but the code is still better on the whole. There are a few regressions being tracked (PR21137, PR21138, PR21139) but by and large this is expected to be a win for x86 generated code performance. It is also more correct than the code it replaces. I have fuzz tested this extensively with ISA extensions up through AVX2 and found no crashes or miscompiles (yet...). The old lowering had a few miscompiles and crashers after a somewhat smaller amount of fuzz testing. There is one significant area where the new code path lags behind and that is in AVX-512 support. However, there was *extremely little* support for that already and so this isn't a significant step backwards and the new framework will probably make it easier to implement lowering that uses the full power of AVX-512's table-based shuffle+blend (IMO). Many thanks to Quentin, Andrea, Robert, and others for benchmarking assistance. Thanks to Adam and others for help with AVX-512. Thanks to Hal, Eric, and *many* others for answering my incessant questions about how the backend actually works. =] I will leave the old code path in the tree until the 3 PRs above are at least resolved to folks' satisfaction. Then I will rip it (and 1000s of lines of code) out. =] I don't expect this flag to stay around for very long. It may not survive next week. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219046 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
2.0 KiB
LLVM
50 lines
2.0 KiB
LLVM
; Tests for SSE1 and below, without SSE2+.
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; RUN: llc < %s -mtriple=i386-unknown-unknown -march=x86 -mcpu=pentium3 -O3 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64 -mattr=-sse2,+sse -O3 | FileCheck %s
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; PR7993
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;define <4 x i32> @test3(<4 x i16> %a) nounwind {
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; %c = sext <4 x i16> %a to <4 x i32> ; <<4 x i32>> [#uses=1]
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; ret <4 x i32> %c
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;}
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; This should not emit shuffles to populate the top 2 elements of the 4-element
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; vector that this ends up returning.
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; rdar://8368414
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define <2 x float> @test4(<2 x float> %A, <2 x float> %B) nounwind {
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; CHECK-LABEL: test4:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movaps %xmm0, %xmm2
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; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]
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; CHECK-NEXT: addss %xmm1, %xmm0
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; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; CHECK-NEXT: subss %xmm1, %xmm2
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; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; CHECK-NEXT: ret
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entry:
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%tmp7 = extractelement <2 x float> %A, i32 0
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%tmp5 = extractelement <2 x float> %A, i32 1
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%tmp3 = extractelement <2 x float> %B, i32 0
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%tmp1 = extractelement <2 x float> %B, i32 1
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%add.r = fadd float %tmp7, %tmp3
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%add.i = fsub float %tmp5, %tmp1
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%tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
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%tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
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ret <2 x float> %tmp9
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}
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; We used to get stuck in type legalization for this example when lowering the
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; vselect. With SSE1 v4f32 is a legal type but v4i1 (or any vector integer type)
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; is not. We used to ping pong between splitting the vselect for the v4i
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; condition operand and widening the resulting vselect for the v4f32 result.
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; PR18036
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define <4 x float> @vselect(<4 x float>*%p, <4 x i32> %q) {
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; CHECK-LABEL: vselect:
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; CHECK: ret
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entry:
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%a1 = icmp eq <4 x i32> %q, zeroinitializer
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%a14 = select <4 x i1> %a1, <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+0> , <4 x float> zeroinitializer
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ret <4 x float> %a14
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}
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