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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
31 lines
1.7 KiB
LLVM
31 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=i686-linux -mcpu=corei7 -x86-asm-syntax=att | FileCheck %s -check-prefix=ATT
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; RUN: llc < %s -mtriple=i686-linux -mcpu=corei7 -x86-asm-syntax=intel | FileCheck %s -check-prefix=INTEL
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target datalayout = "e-p:32:32"
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%struct.Macroblock = type { i32, i32, i32, i32, i32, [8 x i32], %struct.Macroblock*, %struct.Macroblock*, i32, [2 x [4 x [4 x [2 x i32]]]], [16 x i8], [16 x i8], i32, i64, [4 x i32], [4 x i32], i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, double, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
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define internal fastcc i32 @dct_chroma(i32 %uv, i32 %cr_cbp) nounwind {
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cond_true2732.preheader: ; preds = %entry
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%tmp2666 = getelementptr %struct.Macroblock, %struct.Macroblock* null, i32 0, i32 13 ; <i64*> [#uses=2]
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%tmp2674 = trunc i32 0 to i8 ; <i8> [#uses=1]
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%tmp2667.us.us = load i64, i64* %tmp2666 ; <i64> [#uses=1]
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%tmp2670.us.us = load i64, i64* null ; <i64> [#uses=1]
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%shift.upgrd.1 = zext i8 %tmp2674 to i64 ; <i64> [#uses=1]
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%tmp2675.us.us = shl i64 %tmp2670.us.us, %shift.upgrd.1 ; <i64> [#uses=1]
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%tmp2675not.us.us = xor i64 %tmp2675.us.us, -1 ; <i64> [#uses=1]
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%tmp2676.us.us = and i64 %tmp2667.us.us, %tmp2675not.us.us ; <i64> [#uses=1]
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store i64 %tmp2676.us.us, i64* %tmp2666
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ret i32 0
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; INTEL: and {{e..}}, dword ptr [360]
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; INTEL: and dword ptr [356], {{e..}}
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; FIXME: mov dword ptr [360], {{e..}}
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; The above line comes out as 'mov 360, eax', but when the register is ecx it works?
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; ATT: andl 360, %{{e..}}
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; ATT: andl %{{e..}}, 356
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; ATT: movl %{{e..}}, 360
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}
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