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https://github.com/c64scene-ar/llvm-6502.git
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137e1f3f28
We want to replace as much custom x86 shuffling via intrinsics as possible because pushing the code down the generic shuffle optimization path allows for better codegen and less complexity in LLVM. This is the sibling patch for the Clang half of this change: http://reviews.llvm.org/D8088 Differential Revision: http://reviews.llvm.org/D8086 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231794 91177308-0d34-0410-b5e6-96231b3b80d8
237 lines
7.5 KiB
LLVM
237 lines
7.5 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s --check-prefix=SANDYB --check-prefix=CHECK
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx-i | FileCheck %s --check-prefix=SANDYB --check-prefix=CHECK
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=btver2 | FileCheck %s --check-prefix=BTVER2 --check-prefix=CHECK
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 | FileCheck %s --check-prefix=HASWELL --check-prefix=CHECK
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; On Sandy Bridge or Ivy Bridge, we should not generate an unaligned 32-byte load
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; because that is slower than two 16-byte loads.
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; Other AVX-capable chips don't have that problem.
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define <8 x float> @load32bytes(<8 x float>* %Ap) {
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; CHECK-LABEL: load32bytes
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; SANDYB: vmovaps
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; SANDYB: vinsertf128
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; SANDYB: retq
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; BTVER2: vmovups
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; BTVER2: retq
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; HASWELL: vmovups
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; HASWELL: retq
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%A = load <8 x float>, <8 x float>* %Ap, align 16
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ret <8 x float> %A
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}
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; On Sandy Bridge or Ivy Bridge, we should not generate an unaligned 32-byte store
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; because that is slowerthan two 16-byte stores.
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; Other AVX-capable chips don't have that problem.
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define void @store32bytes(<8 x float> %A, <8 x float>* %P) {
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; CHECK-LABEL: store32bytes
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; SANDYB: vextractf128
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; SANDYB: vmovaps
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; SANDYB: retq
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; BTVER2: vmovups
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; BTVER2: retq
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; HASWELL: vmovups
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; HASWELL: retq
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store <8 x float> %A, <8 x float>* %P, align 16
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ret void
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}
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; Merge two consecutive 16-byte subvector loads into a single 32-byte load
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; if it's faster.
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define <8 x float> @combine_16_byte_loads_no_intrinsic(<4 x float>* %ptr) {
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; CHECK-LABEL: combine_16_byte_loads_no_intrinsic
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; SANDYB: vmovups
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; SANDYB-NEXT: vinsertf128
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; SANDYB-NEXT: retq
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; BTVER2: vmovups
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; BTVER2-NEXT: retq
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; HASWELL: vmovups
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; HASWELL-NEXT: retq
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%ptr1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64 3
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%ptr2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64 4
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%v1 = load <4 x float>, <4 x float>* %ptr1, align 1
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%v2 = load <4 x float>, <4 x float>* %ptr2, align 1
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%v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x float> %v3
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}
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; Swap the order of the shufflevector operands to ensure that the
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; pattern still matches.
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define <8 x float> @combine_16_byte_loads_no_intrinsic_swap(<4 x float>* %ptr) {
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; CHECK-LABEL: combine_16_byte_loads_no_intrinsic_swap
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; SANDYB: vmovups
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; SANDYB-NEXT: vinsertf128
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; SANDYB-NEXT: retq
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; BTVER2: vmovups
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; BTVER2-NEXT: retq
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; HASWELL: vmovups
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; HASWELL-NEXT: retq
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%ptr1 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64 4
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%ptr2 = getelementptr inbounds <4 x float>, <4 x float>* %ptr, i64 5
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%v1 = load <4 x float>, <4 x float>* %ptr1, align 1
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%v2 = load <4 x float>, <4 x float>* %ptr2, align 1
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%v3 = shufflevector <4 x float> %v2, <4 x float> %v1, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
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ret <8 x float> %v3
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}
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; Check each element type other than float to make sure it is handled correctly.
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; Use the loaded values with an 'add' to make sure we're using the correct load type.
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; Even though BtVer2 has fast 32-byte loads, we should not generate those for
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; 256-bit integer vectors because BtVer2 doesn't have AVX2.
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define <4 x i64> @combine_16_byte_loads_i64(<2 x i64>* %ptr, <4 x i64> %x) {
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; CHECK-LABEL: combine_16_byte_loads_i64
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; SANDYB: vextractf128
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; SANDYB-NEXT: vpaddq
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; SANDYB-NEXT: vpaddq
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; SANDYB-NEXT: vinsertf128
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; SANDYB-NEXT: retq
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; BTVER2: vextractf128
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; BTVER2-NEXT: vpaddq
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; BTVER2-NEXT: vpaddq
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; BTVER2-NEXT: vinsertf128
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; BTVER2-NEXT: retq
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; HASWELL-NOT: vextract
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; HASWELL: vpaddq
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; HASWELL-NEXT: retq
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%ptr1 = getelementptr inbounds <2 x i64>, <2 x i64>* %ptr, i64 5
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%ptr2 = getelementptr inbounds <2 x i64>, <2 x i64>* %ptr, i64 6
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%v1 = load <2 x i64>, <2 x i64>* %ptr1, align 1
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%v2 = load <2 x i64>, <2 x i64>* %ptr2, align 1
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%v3 = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%v4 = add <4 x i64> %v3, %x
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ret <4 x i64> %v4
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}
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define <8 x i32> @combine_16_byte_loads_i32(<4 x i32>* %ptr, <8 x i32> %x) {
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; CHECK-LABEL: combine_16_byte_loads_i32
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; SANDYB: vextractf128
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; SANDYB-NEXT: vpaddd
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; SANDYB-NEXT: vpaddd
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; SANDYB-NEXT: vinsertf128
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; SANDYB-NEXT: retq
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; BTVER2: vextractf128
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; BTVER2-NEXT: vpaddd
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; BTVER2-NEXT: vpaddd
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; BTVER2-NEXT: vinsertf128
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; BTVER2-NEXT: retq
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; HASWELL-NOT: vextract
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; HASWELL: vpaddd
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; HASWELL-NEXT: retq
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%ptr1 = getelementptr inbounds <4 x i32>, <4 x i32>* %ptr, i64 6
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%ptr2 = getelementptr inbounds <4 x i32>, <4 x i32>* %ptr, i64 7
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%v1 = load <4 x i32>, <4 x i32>* %ptr1, align 1
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%v2 = load <4 x i32>, <4 x i32>* %ptr2, align 1
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%v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%v4 = add <8 x i32> %v3, %x
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ret <8 x i32> %v4
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}
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define <16 x i16> @combine_16_byte_loads_i16(<8 x i16>* %ptr, <16 x i16> %x) {
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; CHECK-LABEL: combine_16_byte_loads_i16
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; SANDYB: vextractf128
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; SANDYB-NEXT: vpaddw
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; SANDYB-NEXT: vpaddw
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; SANDYB-NEXT: vinsertf128
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; SANDYB-NEXT: retq
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; BTVER2: vextractf128
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; BTVER2-NEXT: vpaddw
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; BTVER2-NEXT: vpaddw
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; BTVER2-NEXT: vinsertf128
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; BTVER2-NEXT: retq
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; HASWELL-NOT: vextract
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; HASWELL: vpaddw
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; HASWELL-NEXT: retq
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%ptr1 = getelementptr inbounds <8 x i16>, <8 x i16>* %ptr, i64 7
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%ptr2 = getelementptr inbounds <8 x i16>, <8 x i16>* %ptr, i64 8
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%v1 = load <8 x i16>, <8 x i16>* %ptr1, align 1
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%v2 = load <8 x i16>, <8 x i16>* %ptr2, align 1
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%v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%v4 = add <16 x i16> %v3, %x
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ret <16 x i16> %v4
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}
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define <32 x i8> @combine_16_byte_loads_i8(<16 x i8>* %ptr, <32 x i8> %x) {
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; CHECK-LABEL: combine_16_byte_loads_i8
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; SANDYB: vextractf128
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; SANDYB-NEXT: vpaddb
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; SANDYB-NEXT: vpaddb
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; SANDYB-NEXT: vinsertf128
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; SANDYB-NEXT: retq
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; BTVER2: vextractf128
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; BTVER2-NEXT: vpaddb
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; BTVER2-NEXT: vpaddb
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; BTVER2-NEXT: vinsertf128
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; BTVER2-NEXT: retq
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; HASWELL-NOT: vextract
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; HASWELL: vpaddb
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; HASWELL-NEXT: retq
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%ptr1 = getelementptr inbounds <16 x i8>, <16 x i8>* %ptr, i64 8
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%ptr2 = getelementptr inbounds <16 x i8>, <16 x i8>* %ptr, i64 9
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%v1 = load <16 x i8>, <16 x i8>* %ptr1, align 1
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%v2 = load <16 x i8>, <16 x i8>* %ptr2, align 1
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%v3 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
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%v4 = add <32 x i8> %v3, %x
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ret <32 x i8> %v4
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}
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define <4 x double> @combine_16_byte_loads_double(<2 x double>* %ptr, <4 x double> %x) {
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; CHECK-LABEL: combine_16_byte_loads_double
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; SANDYB: vmovupd
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; SANDYB-NEXT: vinsertf128
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; SANDYB-NEXT: vaddpd
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; SANDYB-NEXT: retq
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; BTVER2-NOT: vinsertf128
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; BTVER2: vaddpd
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; BTVER2-NEXT: retq
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; HASWELL-NOT: vinsertf128
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; HASWELL: vaddpd
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; HASWELL-NEXT: retq
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%ptr1 = getelementptr inbounds <2 x double>, <2 x double>* %ptr, i64 9
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%ptr2 = getelementptr inbounds <2 x double>, <2 x double>* %ptr, i64 10
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%v1 = load <2 x double>, <2 x double>* %ptr1, align 1
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%v2 = load <2 x double>, <2 x double>* %ptr2, align 1
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%v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%v4 = fadd <4 x double> %v3, %x
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ret <4 x double> %v4
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}
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