mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
e3e5fcab94
This is a 1-line patch (with a TODO for AVX because that will affect even more regression tests) that lets us substitute the appropriate 64-bit store for the float/double/int domains. It's not clear to me exactly what the difference is between the 0xD6 (MOVPQI2QImr) and 0x7E (MOVSDto64mr) opcodes, but this is apparently the right choice. Differential Revision: http://reviews.llvm.org/D8691 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235014 91177308-0d34-0410-b5e6-96231b3b80d8
107 lines
4.3 KiB
LLVM
107 lines
4.3 KiB
LLVM
; RUN: llc < %s -march=x86 -mattr=+sse2,+ssse3 | FileCheck %s
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; There are no MMX operations in @t1
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define void @t1(i32 %a, x86_mmx* %P) nounwind {
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; CHECK-LABEL: t1:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: shll $12, %ecx
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; CHECK-NEXT: movd %ecx, %xmm0
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
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; CHECK-NEXT: movq %xmm0, (%eax)
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; CHECK-NEXT: retl
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%tmp12 = shl i32 %a, 12
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%tmp21 = insertelement <2 x i32> undef, i32 %tmp12, i32 1
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%tmp22 = insertelement <2 x i32> %tmp21, i32 0, i32 0
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%tmp23 = bitcast <2 x i32> %tmp22 to x86_mmx
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store x86_mmx %tmp23, x86_mmx* %P
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ret void
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}
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define <4 x float> @t2(<4 x float>* %P) nounwind {
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; CHECK-LABEL: t2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movaps (%eax), %xmm1
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
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; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
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; CHECK-NEXT: retl
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%tmp1 = load <4 x float>, <4 x float>* %P
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 4, i32 4, i32 4, i32 0 >
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ret <4 x float> %tmp2
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}
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define <4 x float> @t3(<4 x float>* %P) nounwind {
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; CHECK-LABEL: t3:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movapd (%eax), %xmm0
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; CHECK-NEXT: xorpd %xmm1, %xmm1
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; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
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; CHECK-NEXT: retl
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%tmp1 = load <4 x float>, <4 x float>* %P
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 2, i32 3, i32 4, i32 4 >
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ret <4 x float> %tmp2
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}
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define <4 x float> @t4(<4 x float>* %P) nounwind {
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; CHECK-LABEL: t4:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movaps (%eax), %xmm0
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; CHECK-NEXT: xorps %xmm1, %xmm1
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; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[1,0]
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; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
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; CHECK-NEXT: retl
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%tmp1 = load <4 x float>, <4 x float>* %P
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%tmp2 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp1, <4 x i32> < i32 7, i32 0, i32 0, i32 0 >
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ret <4 x float> %tmp2
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}
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define <16 x i8> @t5(<16 x i8> %x) nounwind {
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; CHECK-LABEL: t5:
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; CHECK: # BB#0:
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; CHECK-NEXT: psrlw $8, %xmm0
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; CHECK-NEXT: retl
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%s = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 17>
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ret <16 x i8> %s
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}
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define <16 x i8> @t6(<16 x i8> %x) nounwind {
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; CHECK-LABEL: t6:
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; CHECK: # BB#0:
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; CHECK-NEXT: psrlw $8, %xmm0
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; CHECK-NEXT: retl
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%s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <16 x i8> %s
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}
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define <16 x i8> @t7(<16 x i8> %x) nounwind {
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; CHECK-LABEL: t7:
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; CHECK: # BB#0:
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; CHECK-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2]
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; CHECK-NEXT: retl
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%s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2>
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ret <16 x i8> %s
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}
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define <16 x i8> @t8(<16 x i8> %x) nounwind {
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; CHECK-LABEL: t8:
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; CHECK: # BB#0:
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; CHECK-NEXT: psrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
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; CHECK-NEXT: retl
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%s = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 17>
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ret <16 x i8> %s
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}
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define <16 x i8> @t9(<16 x i8> %x) nounwind {
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; CHECK-LABEL: t9:
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; CHECK: # BB#0:
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; CHECK-NEXT: psrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
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; CHECK-NEXT: retl
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%s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 7, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 14, i32 undef, i32 undef>
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ret <16 x i8> %s
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}
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