Nate Begeman af4ab1b103 Optimize FSEL a bit for fneg arguments. This fixes the recently added test ... case so that we emit _test_fneg_sel: .LBB_test_fneg_sel_0: ; fsel f1, f1, f3, f2 blr instead of: _test_fneg_sel: .LBB_test_fneg_sel_0: ; fneg f0, f1 fneg f0, f0 fsel f1, f0, f3, f2 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21177 91177308-0d34-0410-b5e6-96231b3b80d8		2005-04-09 09:33:07 +00:00
..
Alpha	This target does not support/want ISD::BRCONDTWOWAY	2005-04-09 03:22:37 +00:00
CBackend
IA64	This target does not support/want ISD::BRCONDTWOWAY	2005-04-09 03:22:37 +00:00
PowerPC	Optimize FSEL a bit for fneg arguments. This fixes the recently added test	2005-04-09 09:33:07 +00:00
Skeleton
Sparc
SparcV8
SparcV9	Fix CodeGen/SparcV9/2005-05-09-GEP-Crash.ll a crash on some specfp program	2005-04-09 06:27:14 +00:00
X86	This target does not support/want ISD::BRCONDTWOWAY	2005-04-09 03:22:37 +00:00
Makefile
MRegisterInfo.cpp
Target.td
TargetData.cpp
TargetFrameInfo.cpp
TargetInstrInfo.cpp
TargetMachine.cpp
TargetMachineRegistry.cpp
TargetSchedInfo.cpp