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https://github.com/c64scene-ar/llvm-6502.git
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af70e5c676
leads to partial-register definitions. To help avoid redundant zero-extensions, also teach the h-register matching patterns that use movzbl to match anyext as well as zext. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80099 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
792 B
LLVM
25 lines
792 B
LLVM
; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 3
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define fastcc i32 @sqlite3ExprResolveNames() nounwind {
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entry:
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br i1 false, label %UnifiedReturnBlock, label %bb4
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bb4: ; preds = %entry
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br i1 false, label %bb17, label %bb22
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bb17: ; preds = %bb4
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ret i32 1
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bb22: ; preds = %bb4
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br i1 true, label %walkExprTree.exit, label %bb4.i
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bb4.i: ; preds = %bb22
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ret i32 0
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walkExprTree.exit: ; preds = %bb22
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%tmp83 = load i16* null, align 4 ; <i16> [#uses=1]
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%tmp84 = or i16 %tmp83, 2 ; <i16> [#uses=2]
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store i16 %tmp84, i16* null, align 4
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%tmp98993 = zext i16 %tmp84 to i32 ; <i32> [#uses=1]
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%tmp1004 = lshr i32 %tmp98993, 3 ; <i32> [#uses=1]
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%tmp100.lobit5 = and i32 %tmp1004, 1 ; <i32> [#uses=1]
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ret i32 %tmp100.lobit5
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UnifiedReturnBlock: ; preds = %entry
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ret i32 0
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}
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