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LLVM backend for 6502
if we don't have an address expression available in a predecessor, then model this as the value being clobbered at the end of the pred block instead of being modeled as a complete phi translation failure. This is important for PRE of loads because we want to see that the load is available in all but this predecessor, and complete phi translation failure results in not getting any information about predecessors. This doesn't do anything until I renable code insertion since PRE now sees that it is available in all but one predecessors, but can't insert the addressing in the predecessor that is missing it to eliminate the redundancy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90037 91177308-0d34-0410-b5e6-96231b3b80d8 |
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