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Variadic MC instructions don't note whether the variable operands are uses or defs, so mayAffectControlFlow() must conservatively assume they are defs and return true if the PC is in the operand list. rdar://14488628 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186846 91177308-0d34-0410-b5e6-96231b3b80d8
577 lines
22 KiB
C++
577 lines
22 KiB
C++
//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MCOperandInfo and MCInstrDesc classes, which
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// are used to describe target instructions and their operands.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCINSTRDESC_H
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#define LLVM_MC_MCINSTRDESC_H
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/DataTypes.h"
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namespace llvm {
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//===----------------------------------------------------------------------===//
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// Machine Operand Flags and Description
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//===----------------------------------------------------------------------===//
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namespace MCOI {
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// Operand constraints
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enum OperandConstraint {
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TIED_TO = 0, // Must be allocated the same register as.
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EARLY_CLOBBER // Operand is an early clobber register operand
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};
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/// OperandFlags - These are flags set on operands, but should be considered
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/// private, all access should go through the MCOperandInfo accessors.
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/// See the accessors for a description of what these are.
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enum OperandFlags {
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LookupPtrRegClass = 0,
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Predicate,
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OptionalDef
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};
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/// Operand Type - Operands are tagged with one of the values of this enum.
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enum OperandType {
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OPERAND_UNKNOWN,
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OPERAND_IMMEDIATE,
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OPERAND_REGISTER,
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OPERAND_MEMORY,
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OPERAND_PCREL
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};
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}
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/// MCOperandInfo - This holds information about one operand of a machine
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/// instruction, indicating the register class for register operands, etc.
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///
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class MCOperandInfo {
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public:
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/// RegClass - This specifies the register class enumeration of the operand
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/// if the operand is a register. If isLookupPtrRegClass is set, then this is
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/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
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/// get a dynamic register class.
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int16_t RegClass;
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/// Flags - These are flags from the MCOI::OperandFlags enum.
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uint8_t Flags;
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/// OperandType - Information about the type of the operand.
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uint8_t OperandType;
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/// Lower 16 bits are used to specify which constraints are set. The higher 16
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/// bits are used to specify the value of constraints (4 bits each).
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uint32_t Constraints;
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/// Currently no other information.
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/// isLookupPtrRegClass - Set if this operand is a pointer value and it
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/// requires a callback to look up its register class.
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bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
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/// isPredicate - Set if this is one of the operands that made up of
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/// the predicate operand that controls an isPredicable() instruction.
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bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
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/// isOptionalDef - Set if this operand is a optional def.
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///
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bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
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};
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//===----------------------------------------------------------------------===//
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// Machine Instruction Flags and Description
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//===----------------------------------------------------------------------===//
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/// MCInstrDesc flags - These should be considered private to the
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/// implementation of the MCInstrDesc class. Clients should use the predicate
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/// methods on MCInstrDesc, not use these directly. These all correspond to
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/// bitfields in the MCInstrDesc::Flags field.
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namespace MCID {
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enum {
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Variadic = 0,
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HasOptionalDef,
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Pseudo,
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Return,
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Call,
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Barrier,
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Terminator,
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Branch,
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IndirectBranch,
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Compare,
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MoveImm,
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Bitcast,
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Select,
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DelaySlot,
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FoldableAsLoad,
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MayLoad,
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MayStore,
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Predicable,
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NotDuplicable,
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UnmodeledSideEffects,
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Commutable,
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ConvertibleTo3Addr,
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UsesCustomInserter,
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HasPostISelHook,
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Rematerializable,
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CheapAsAMove,
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ExtraSrcRegAllocReq,
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ExtraDefRegAllocReq
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};
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}
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/// MCInstrDesc - Describe properties that are true of each instruction in the
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/// target description file. This captures information about side effects,
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/// register use and many other things. There is one instance of this struct
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/// for each target instruction class, and the MachineInstr class points to
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/// this struct directly to describe itself.
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class MCInstrDesc {
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public:
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unsigned short Opcode; // The opcode number
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unsigned short NumOperands; // Num of args (may be more if variable_ops)
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unsigned short NumDefs; // Num of args that are definitions
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unsigned short SchedClass; // enum identifying instr sched class
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unsigned short Size; // Number of bytes in encoding.
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unsigned Flags; // Flags identifying machine instr class
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uint64_t TSFlags; // Target Specific Flag values
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const uint16_t *ImplicitUses; // Registers implicitly read by this instr
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const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
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const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
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/// \brief Returns the value of the specific constraint if
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/// it is set. Returns -1 if it is not set.
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int getOperandConstraint(unsigned OpNum,
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MCOI::OperandConstraint Constraint) const {
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if (OpNum < NumOperands &&
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(OpInfo[OpNum].Constraints & (1 << Constraint))) {
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unsigned Pos = 16 + Constraint * 4;
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return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
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}
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return -1;
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}
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/// \brief Return the opcode number for this descriptor.
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unsigned getOpcode() const {
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return Opcode;
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}
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/// \brief Return the number of declared MachineOperands for this
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/// MachineInstruction. Note that variadic (isVariadic() returns true)
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/// instructions may have additional operands at the end of the list, and note
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/// that the machine instruction may include implicit register def/uses as
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/// well.
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unsigned getNumOperands() const {
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return NumOperands;
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}
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/// \brief Return the number of MachineOperands that are register
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/// definitions. Register definitions always occur at the start of the
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/// machine operand list. This is the number of "outs" in the .td file,
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/// and does not include implicit defs.
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unsigned getNumDefs() const {
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return NumDefs;
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}
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/// \brief Return flags of this instruction.
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unsigned getFlags() const { return Flags; }
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/// \brief Return true if this instruction can have a variable number of
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/// operands. In this case, the variable operands will be after the normal
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/// operands but before the implicit definitions and uses (if any are
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/// present).
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bool isVariadic() const {
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return Flags & (1 << MCID::Variadic);
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}
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/// \brief Set if this instruction has an optional definition, e.g.
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/// ARM instructions which can set condition code if 's' bit is set.
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bool hasOptionalDef() const {
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return Flags & (1 << MCID::HasOptionalDef);
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}
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/// \brief Return true if this is a pseudo instruction that doesn't
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/// correspond to a real machine instruction.
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///
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bool isPseudo() const {
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return Flags & (1 << MCID::Pseudo);
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}
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/// \brief Return true if the instruction is a return.
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bool isReturn() const {
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return Flags & (1 << MCID::Return);
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}
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/// \brief Return true if the instruction is a call.
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bool isCall() const {
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return Flags & (1 << MCID::Call);
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}
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/// \brief Returns true if the specified instruction stops control flow
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/// from executing the instruction immediately following it. Examples include
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/// unconditional branches and return instructions.
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bool isBarrier() const {
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return Flags & (1 << MCID::Barrier);
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}
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/// \brief Returns true if this instruction part of the terminator for
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/// a basic block. Typically this is things like return and branch
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/// instructions.
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///
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/// Various passes use this to insert code into the bottom of a basic block,
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/// but before control flow occurs.
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bool isTerminator() const {
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return Flags & (1 << MCID::Terminator);
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}
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/// \brief Returns true if this is a conditional, unconditional, or
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/// indirect branch. Predicates below can be used to discriminate between
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/// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
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/// get more information.
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bool isBranch() const {
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return Flags & (1 << MCID::Branch);
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}
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/// \brief Return true if this is an indirect branch, such as a
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/// branch through a register.
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bool isIndirectBranch() const {
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return Flags & (1 << MCID::IndirectBranch);
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}
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/// \brief Return true if this is a branch which may fall
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/// through to the next instruction or may transfer control flow to some other
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/// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
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/// information about this branch.
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bool isConditionalBranch() const {
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return isBranch() & !isBarrier() & !isIndirectBranch();
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}
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/// \brief Return true if this is a branch which always
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/// transfers control flow to some other block. The
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/// TargetInstrInfo::AnalyzeBranch method can be used to get more information
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/// about this branch.
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bool isUnconditionalBranch() const {
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return isBranch() & isBarrier() & !isIndirectBranch();
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}
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/// \brief Return true if this is a branch or an instruction which directly
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/// writes to the program counter. Considered 'may' affect rather than
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/// 'does' affect as things like predication are not taken into account.
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bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const {
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if (isBranch() || isCall() || isReturn() || isIndirectBranch())
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return true;
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unsigned PC = RI.getProgramCounter();
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if (PC == 0)
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return false;
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if (hasDefOfPhysReg(MI, PC, RI))
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return true;
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// A variadic instruction may define PC in the variable operand list.
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// There's currently no indication of which entries in a variable
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// list are defs and which are uses. While that's the case, this function
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// needs to assume they're defs in order to be conservatively correct.
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for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
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if (MI.getOperand(i).isReg() &&
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RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
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return true;
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}
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return false;
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}
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/// \brief Return true if this instruction has a predicate operand
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/// that controls execution. It may be set to 'always', or may be set to other
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/// values. There are various methods in TargetInstrInfo that can be used to
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/// control and modify the predicate in this instruction.
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bool isPredicable() const {
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return Flags & (1 << MCID::Predicable);
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}
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/// \brief Return true if this instruction is a comparison.
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bool isCompare() const {
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return Flags & (1 << MCID::Compare);
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}
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/// \brief Return true if this instruction is a move immediate
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/// (including conditional moves) instruction.
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bool isMoveImmediate() const {
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return Flags & (1 << MCID::MoveImm);
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}
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/// \brief Return true if this instruction is a bitcast instruction.
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bool isBitcast() const {
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return Flags & (1 << MCID::Bitcast);
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}
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/// \brief Return true if this is a select instruction.
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bool isSelect() const {
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return Flags & (1 << MCID::Select);
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}
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/// \brief Return true if this instruction cannot be safely
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/// duplicated. For example, if the instruction has a unique labels attached
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/// to it, duplicating it would cause multiple definition errors.
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bool isNotDuplicable() const {
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return Flags & (1 << MCID::NotDuplicable);
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}
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/// hasDelaySlot - Returns true if the specified instruction has a delay slot
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/// which must be filled by the code generator.
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bool hasDelaySlot() const {
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return Flags & (1 << MCID::DelaySlot);
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}
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/// canFoldAsLoad - Return true for instructions that can be folded as
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/// memory operands in other instructions. The most common use for this
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/// is instructions that are simple loads from memory that don't modify
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/// the loaded value in any way, but it can also be used for instructions
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/// that can be expressed as constant-pool loads, such as V_SETALLONES
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/// on x86, to allow them to be folded when it is beneficial.
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/// This should only be set on instructions that return a value in their
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/// only virtual register definition.
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bool canFoldAsLoad() const {
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return Flags & (1 << MCID::FoldableAsLoad);
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}
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//===--------------------------------------------------------------------===//
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// Side Effect Analysis
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//===--------------------------------------------------------------------===//
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/// \brief Return true if this instruction could possibly read memory.
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/// Instructions with this flag set are not necessarily simple load
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/// instructions, they may load a value and modify it, for example.
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bool mayLoad() const {
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return Flags & (1 << MCID::MayLoad);
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}
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/// \brief Return true if this instruction could possibly modify memory.
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/// Instructions with this flag set are not necessarily simple store
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/// instructions, they may store a modified value based on their operands, or
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/// may not actually modify anything, for example.
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bool mayStore() const {
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return Flags & (1 << MCID::MayStore);
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}
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/// hasUnmodeledSideEffects - Return true if this instruction has side
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/// effects that are not modeled by other flags. This does not return true
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/// for instructions whose effects are captured by:
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///
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/// 1. Their operand list and implicit definition/use list. Register use/def
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/// info is explicit for instructions.
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/// 2. Memory accesses. Use mayLoad/mayStore.
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/// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
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///
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/// Examples of side effects would be modifying 'invisible' machine state like
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/// a control register, flushing a cache, modifying a register invisible to
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/// LLVM, etc.
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///
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bool hasUnmodeledSideEffects() const {
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return Flags & (1 << MCID::UnmodeledSideEffects);
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}
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//===--------------------------------------------------------------------===//
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// Flags that indicate whether an instruction can be modified by a method.
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//===--------------------------------------------------------------------===//
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/// isCommutable - Return true if this may be a 2- or 3-address
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/// instruction (of the form "X = op Y, Z, ..."), which produces the same
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/// result if Y and Z are exchanged. If this flag is set, then the
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/// TargetInstrInfo::commuteInstruction method may be used to hack on the
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/// instruction.
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///
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/// Note that this flag may be set on instructions that are only commutable
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/// sometimes. In these cases, the call to commuteInstruction will fail.
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/// Also note that some instructions require non-trivial modification to
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/// commute them.
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bool isCommutable() const {
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return Flags & (1 << MCID::Commutable);
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}
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/// isConvertibleTo3Addr - Return true if this is a 2-address instruction
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/// which can be changed into a 3-address instruction if needed. Doing this
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/// transformation can be profitable in the register allocator, because it
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/// means that the instruction can use a 2-address form if possible, but
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/// degrade into a less efficient form if the source and dest register cannot
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/// be assigned to the same register. For example, this allows the x86
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/// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
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/// is the same speed as the shift but has bigger code size.
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///
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/// If this returns true, then the target must implement the
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/// TargetInstrInfo::convertToThreeAddress method for this instruction, which
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/// is allowed to fail if the transformation isn't valid for this specific
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/// instruction (e.g. shl reg, 4 on x86).
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///
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bool isConvertibleTo3Addr() const {
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return Flags & (1 << MCID::ConvertibleTo3Addr);
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}
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/// usesCustomInsertionHook - Return true if this instruction requires
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/// custom insertion support when the DAG scheduler is inserting it into a
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/// machine basic block. If this is true for the instruction, it basically
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/// means that it is a pseudo instruction used at SelectionDAG time that is
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/// expanded out into magic code by the target when MachineInstrs are formed.
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///
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/// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
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/// is used to insert this into the MachineBasicBlock.
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bool usesCustomInsertionHook() const {
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return Flags & (1 << MCID::UsesCustomInserter);
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}
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/// hasPostISelHook - Return true if this instruction requires *adjustment*
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/// after instruction selection by calling a target hook. For example, this
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/// can be used to fill in ARM 's' optional operand depending on whether
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/// the conditional flag register is used.
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bool hasPostISelHook() const {
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return Flags & (1 << MCID::HasPostISelHook);
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}
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/// isRematerializable - Returns true if this instruction is a candidate for
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/// remat. This flag is deprecated, please don't use it anymore. If this
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/// flag is set, the isReallyTriviallyReMaterializable() method is called to
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/// verify the instruction is really rematable.
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bool isRematerializable() const {
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return Flags & (1 << MCID::Rematerializable);
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}
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/// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
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/// less) than a move instruction. This is useful during certain types of
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/// optimizations (e.g., remat during two-address conversion or machine licm)
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/// where we would like to remat or hoist the instruction, but not if it costs
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/// more than moving the instruction into the appropriate register. Note, we
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/// are not marking copies from and to the same register class with this flag.
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bool isAsCheapAsAMove() const {
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return Flags & (1 << MCID::CheapAsAMove);
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}
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/// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
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/// have special register allocation requirements that are not captured by the
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/// operand register classes. e.g. ARM::STRD's two source registers must be an
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/// even / odd pair, ARM::STM registers have to be in ascending order.
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/// Post-register allocation passes should not attempt to change allocations
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/// for sources of instructions with this flag.
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bool hasExtraSrcRegAllocReq() const {
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return Flags & (1 << MCID::ExtraSrcRegAllocReq);
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}
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/// hasExtraDefRegAllocReq - Returns true if this instruction def operands
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/// have special register allocation requirements that are not captured by the
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/// operand register classes. e.g. ARM::LDRD's two def registers must be an
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/// even / odd pair, ARM::LDM registers have to be in ascending order.
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/// Post-register allocation passes should not attempt to change allocations
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/// for definitions of instructions with this flag.
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bool hasExtraDefRegAllocReq() const {
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return Flags & (1 << MCID::ExtraDefRegAllocReq);
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}
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/// getImplicitUses - Return a list of registers that are potentially
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/// read by any instance of this machine instruction. For example, on X86,
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/// the "adc" instruction adds two register operands and adds the carry bit in
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/// from the flags register. In this case, the instruction is marked as
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/// implicitly reading the flags. Likewise, the variable shift instruction on
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/// X86 is marked as implicitly reading the 'CL' register, which it always
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/// does.
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///
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/// This method returns null if the instruction has no implicit uses.
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const uint16_t *getImplicitUses() const {
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return ImplicitUses;
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}
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|
/// \brief Return the number of implicit uses this instruction has.
|
|
unsigned getNumImplicitUses() const {
|
|
if (ImplicitUses == 0) return 0;
|
|
unsigned i = 0;
|
|
for (; ImplicitUses[i]; ++i) /*empty*/;
|
|
return i;
|
|
}
|
|
|
|
/// getImplicitDefs - Return a list of registers that are potentially
|
|
/// written by any instance of this machine instruction. For example, on X86,
|
|
/// many instructions implicitly set the flags register. In this case, they
|
|
/// are marked as setting the FLAGS. Likewise, many instructions always
|
|
/// deposit their result in a physical register. For example, the X86 divide
|
|
/// instruction always deposits the quotient and remainder in the EAX/EDX
|
|
/// registers. For that instruction, this will return a list containing the
|
|
/// EAX/EDX/EFLAGS registers.
|
|
///
|
|
/// This method returns null if the instruction has no implicit defs.
|
|
const uint16_t *getImplicitDefs() const {
|
|
return ImplicitDefs;
|
|
}
|
|
|
|
/// \brief Return the number of implicit defs this instruct has.
|
|
unsigned getNumImplicitDefs() const {
|
|
if (ImplicitDefs == 0) return 0;
|
|
unsigned i = 0;
|
|
for (; ImplicitDefs[i]; ++i) /*empty*/;
|
|
return i;
|
|
}
|
|
|
|
/// \brief Return true if this instruction implicitly
|
|
/// uses the specified physical register.
|
|
bool hasImplicitUseOfPhysReg(unsigned Reg) const {
|
|
if (const uint16_t *ImpUses = ImplicitUses)
|
|
for (; *ImpUses; ++ImpUses)
|
|
if (*ImpUses == Reg) return true;
|
|
return false;
|
|
}
|
|
|
|
/// \brief Return true if this instruction implicitly
|
|
/// defines the specified physical register.
|
|
bool hasImplicitDefOfPhysReg(unsigned Reg,
|
|
const MCRegisterInfo *MRI = 0) const {
|
|
if (const uint16_t *ImpDefs = ImplicitDefs)
|
|
for (; *ImpDefs; ++ImpDefs)
|
|
if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
/// \brief Return true if this instruction defines the specified physical
|
|
/// register, either explicitly or implicitly.
|
|
bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
|
|
const MCRegisterInfo &RI) const {
|
|
for (int i = 0, e = NumDefs; i != e; ++i)
|
|
if (MI.getOperand(i).isReg() &&
|
|
RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
|
|
return true;
|
|
return hasImplicitDefOfPhysReg(Reg, &RI);
|
|
}
|
|
|
|
/// \brief Return the scheduling class for this instruction. The
|
|
/// scheduling class is an index into the InstrItineraryData table. This
|
|
/// returns zero if there is no known scheduling information for the
|
|
/// instruction.
|
|
unsigned getSchedClass() const {
|
|
return SchedClass;
|
|
}
|
|
|
|
/// \brief Return the number of bytes in the encoding of this instruction,
|
|
/// or zero if the encoding size cannot be known from the opcode.
|
|
unsigned getSize() const {
|
|
return Size;
|
|
}
|
|
|
|
/// \brief Find the index of the first operand in the
|
|
/// operand list that is used to represent the predicate. It returns -1 if
|
|
/// none is found.
|
|
int findFirstPredOperandIdx() const {
|
|
if (isPredicable()) {
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
|
|
if (OpInfo[i].isPredicate())
|
|
return i;
|
|
}
|
|
return -1;
|
|
}
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|