Preston Gurd 6a8c7bf8e7 This patch fixes a problem which arose when using the Post-RA scheduler ... on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8		2012-04-23 21:39:35 +00:00
..
InstPrinter	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
MCTargetDesc	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
TargetInfo
CMakeLists.txt	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
Hexagon.h	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
Hexagon.td	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonAsmPrinter.cpp	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonAsmPrinter.h	Hexagon: enable assembler output through the MC layer.	2012-04-12 17:55:53 +00:00
HexagonCallingConv.td	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonCallingConvLower.cpp	Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.	2012-03-17 18:46:09 +00:00
HexagonCallingConvLower.h
HexagonCFGOptimizer.cpp	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.	2012-02-18 12:03:15 +00:00
HexagonExpandPredSpillCode.cpp	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonFrameLowering.cpp	Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.	2012-03-17 18:46:09 +00:00
HexagonFrameLowering.h
HexagonHardwareLoops.cpp	Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.	2012-04-20 07:30:17 +00:00
HexagonImmediates.td	Hexagon: enable assembler output through the MC layer.	2012-04-12 17:55:53 +00:00
HexagonInstrFormats.td	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonInstrFormatsV4.td	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonInstrInfo.cpp	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonInstrInfo.h	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonInstrInfo.td	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonInstrInfoV3.td	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonInstrInfoV4.td	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonIntrinsics.td	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonIntrinsicsDerived.td	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonIntrinsicsV3.td
HexagonIntrinsicsV4.td
HexagonISelDAGToDAG.cpp	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonISelLowering.cpp	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonISelLowering.h	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonMachineFunctionInfo.h
HexagonMCInstLower.cpp	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonPeephole.cpp	Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.	2012-03-17 18:46:09 +00:00
HexagonRegisterInfo.cpp	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonRegisterInfo.h	This patch fixes a problem which arose when using the Post-RA scheduler	2012-04-23 21:39:35 +00:00
HexagonRegisterInfo.td	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonRemoveSZExtArgs.cpp
HexagonSchedule.td	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonScheduleV4.td	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonSelectCCInfo.td	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.	2012-02-18 12:03:15 +00:00
HexagonSelectionDAGInfo.cpp
HexagonSelectionDAGInfo.h	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.	2012-02-18 12:03:15 +00:00
HexagonSplitTFRCondSets.cpp	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonSubtarget.cpp	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonSubtarget.h	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonTargetMachine.cpp	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
HexagonTargetMachine.h	Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.	2012-03-17 18:46:09 +00:00
HexagonTargetObjectFile.cpp	Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.	2012-03-17 18:46:09 +00:00
HexagonTargetObjectFile.h	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.	2012-02-18 12:03:15 +00:00
HexagonVarargsCallingConvention.h	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.	2012-02-18 12:03:15 +00:00
LLVMBuild.txt	Hexagon: enable assembler output through the MC layer.	2012-04-12 17:55:53 +00:00
Makefile	Hexagon: enable assembler output through the MC layer.	2012-04-12 17:55:53 +00:00