Jim Grosbach afb4ef3549 Add support for load folding of avx1 logical instructions ... AVX supports logical operations using an operand from memory. Unfortunately because integer operations were not added until AVX2 the AVX1 logical operation's types were preventing the isel from folding the loads. In a limited number of cases the peephole optimizer would fold the loads, but most were missed. This patch adds explicit patterns with appropriate casts in order for these loads to be folded. The included test cases run on reduced examples and disable the peephole optimizer to ensure the folds are being pattern matched. Patch by Louis Gerbarg <lgg@apple.com> rdar://16355124 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205938 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-09 23:39:25 +00:00
..
AArch64	[AArch64] Implement the isZExtFree APIs.	2014-04-09 20:51:21 +00:00
ARM
ARM64	[DAGCombiner] DAG combine does not know how to combine indexed loads with	2014-04-09 20:03:05 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math	2014-04-09 09:56:43 +00:00
MSP430
NVPTX	[NVPTX] Add preliminary intrinsics and codegen support for textures/surfaces	2014-04-09 15:39:15 +00:00
PowerPC	[PowerPC] Add a full condition code register to make the "cc" clobber work	2014-04-04 15:15:57 +00:00
R600	R600/SI: Match not instruction.	2014-04-09 07:16:16 +00:00
SPARC
SystemZ
Thumb
Thumb2	ARM: fix test case missed in previous roundup	2014-04-04 01:19:56 +00:00
X86	Add support for load folding of avx1 logical instructions	2014-04-09 23:39:25 +00:00
XCore