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Use information computed while inferring new register classes to emit accurate, table-driven implementations of getMatchingSuperRegClass(). Delete the old manual, error-prone implementations in the targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
991 lines
37 KiB
C++
991 lines
37 KiB
C++
//===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines structures to encapsulate information gleaned from the
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// target register and register class definitions.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenRegisters.h"
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#include "CodeGenTarget.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringExtras.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// CodeGenRegister
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//===----------------------------------------------------------------------===//
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CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
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: TheDef(R),
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EnumValue(Enum),
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CostPerUse(R->getValueAsInt("CostPerUse")),
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SubRegsComplete(false)
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{}
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const std::string &CodeGenRegister::getName() const {
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return TheDef->getName();
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}
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namespace {
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struct Orphan {
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CodeGenRegister *SubReg;
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Record *First, *Second;
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Orphan(CodeGenRegister *r, Record *a, Record *b)
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: SubReg(r), First(a), Second(b) {}
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};
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}
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const CodeGenRegister::SubRegMap &
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CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
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// Only compute this map once.
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if (SubRegsComplete)
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return SubRegs;
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SubRegsComplete = true;
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std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs");
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std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
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if (SubList.size() != Indices.size())
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throw TGError(TheDef->getLoc(), "Register " + getName() +
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" SubRegIndices doesn't match SubRegs");
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// First insert the direct subregs and make sure they are fully indexed.
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for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
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CodeGenRegister *SR = RegBank.getReg(SubList[i]);
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if (!SubRegs.insert(std::make_pair(Indices[i], SR)).second)
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throw TGError(TheDef->getLoc(), "SubRegIndex " + Indices[i]->getName() +
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" appears twice in Register " + getName());
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}
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// Keep track of inherited subregs and how they can be reached.
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SmallVector<Orphan, 8> Orphans;
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// Clone inherited subregs and place duplicate entries on Orphans.
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// Here the order is important - earlier subregs take precedence.
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for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
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CodeGenRegister *SR = RegBank.getReg(SubList[i]);
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const SubRegMap &Map = SR->getSubRegs(RegBank);
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// Add this as a super-register of SR now all sub-registers are in the list.
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// This creates a topological ordering, the exact order depends on the
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// order getSubRegs is called on all registers.
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SR->SuperRegs.push_back(this);
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for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
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++SI) {
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if (!SubRegs.insert(*SI).second)
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Orphans.push_back(Orphan(SI->second, Indices[i], SI->first));
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// Noop sub-register indexes are possible, so avoid duplicates.
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if (SI->second != SR)
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SI->second->SuperRegs.push_back(this);
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}
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}
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// Process the composites.
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ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices");
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for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
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DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
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if (!Pat)
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throw TGError(TheDef->getLoc(), "Invalid dag '" +
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Comps->getElement(i)->getAsString() +
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"' in CompositeIndices");
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DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
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if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
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throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
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Pat->getAsString());
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// Resolve list of subreg indices into R2.
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CodeGenRegister *R2 = this;
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for (DagInit::const_arg_iterator di = Pat->arg_begin(),
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de = Pat->arg_end(); di != de; ++di) {
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DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
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if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
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throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
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Pat->getAsString());
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const SubRegMap &R2Subs = R2->getSubRegs(RegBank);
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SubRegMap::const_iterator ni = R2Subs.find(IdxInit->getDef());
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if (ni == R2Subs.end())
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throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() +
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" refers to bad index in " + R2->getName());
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R2 = ni->second;
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}
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// Insert composite index. Allow overriding inherited indices etc.
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SubRegs[BaseIdxInit->getDef()] = R2;
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// R2 is no longer an orphan.
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for (unsigned j = 0, je = Orphans.size(); j != je; ++j)
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if (Orphans[j].SubReg == R2)
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Orphans[j].SubReg = 0;
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}
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// Now Orphans contains the inherited subregisters without a direct index.
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// Create inferred indexes for all missing entries.
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for (unsigned i = 0, e = Orphans.size(); i != e; ++i) {
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Orphan &O = Orphans[i];
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if (!O.SubReg)
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continue;
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SubRegs[RegBank.getCompositeSubRegIndex(O.First, O.Second, true)] =
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O.SubReg;
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}
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return SubRegs;
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}
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void
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CodeGenRegister::addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const {
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assert(SubRegsComplete && "Must precompute sub-registers");
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std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
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for (unsigned i = 0, e = Indices.size(); i != e; ++i) {
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CodeGenRegister *SR = SubRegs.find(Indices[i])->second;
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if (OSet.insert(SR))
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SR->addSubRegsPreOrder(OSet);
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}
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}
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//===----------------------------------------------------------------------===//
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// RegisterTuples
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//===----------------------------------------------------------------------===//
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// A RegisterTuples def is used to generate pseudo-registers from lists of
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// sub-registers. We provide a SetTheory expander class that returns the new
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// registers.
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namespace {
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struct TupleExpander : SetTheory::Expander {
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void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) {
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std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
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unsigned Dim = Indices.size();
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ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
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if (Dim != SubRegs->getSize())
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throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
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if (Dim < 2)
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throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers");
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// Evaluate the sub-register lists to be zipped.
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unsigned Length = ~0u;
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SmallVector<SetTheory::RecSet, 4> Lists(Dim);
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for (unsigned i = 0; i != Dim; ++i) {
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ST.evaluate(SubRegs->getElement(i), Lists[i]);
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Length = std::min(Length, unsigned(Lists[i].size()));
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}
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if (Length == 0)
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return;
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// Precompute some types.
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Record *RegisterCl = Def->getRecords().getClass("Register");
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RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl);
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StringInit *BlankName = StringInit::get("");
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// Zip them up.
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for (unsigned n = 0; n != Length; ++n) {
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std::string Name;
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Record *Proto = Lists[0][n];
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std::vector<Init*> Tuple;
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unsigned CostPerUse = 0;
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for (unsigned i = 0; i != Dim; ++i) {
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Record *Reg = Lists[i][n];
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if (i) Name += '_';
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Name += Reg->getName();
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Tuple.push_back(DefInit::get(Reg));
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CostPerUse = std::max(CostPerUse,
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unsigned(Reg->getValueAsInt("CostPerUse")));
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}
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// Create a new Record representing the synthesized register. This record
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// is only for consumption by CodeGenRegister, it is not added to the
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// RecordKeeper.
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Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
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Elts.insert(NewReg);
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// Copy Proto super-classes.
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for (unsigned i = 0, e = Proto->getSuperClasses().size(); i != e; ++i)
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NewReg->addSuperClass(Proto->getSuperClasses()[i]);
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// Copy Proto fields.
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for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
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RecordVal RV = Proto->getValues()[i];
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// Replace the sub-register list with Tuple.
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if (RV.getName() == "SubRegs")
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RV.setValue(ListInit::get(Tuple, RegisterRecTy));
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// Provide a blank AsmName. MC hacks are required anyway.
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if (RV.getName() == "AsmName")
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RV.setValue(BlankName);
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// CostPerUse is aggregated from all Tuple members.
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if (RV.getName() == "CostPerUse")
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RV.setValue(IntInit::get(CostPerUse));
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// Copy fields from the RegisterTuples def.
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if (RV.getName() == "SubRegIndices" ||
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RV.getName() == "CompositeIndices") {
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NewReg->addValue(*Def->getValue(RV.getName()));
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continue;
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}
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// Some fields get their default uninitialized value.
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if (RV.getName() == "DwarfNumbers" ||
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RV.getName() == "DwarfAlias" ||
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RV.getName() == "Aliases") {
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if (const RecordVal *DefRV = RegisterCl->getValue(RV.getName()))
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NewReg->addValue(*DefRV);
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continue;
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}
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// Everything else is copied from Proto.
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NewReg->addValue(RV);
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}
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}
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}
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};
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}
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//===----------------------------------------------------------------------===//
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// CodeGenRegisterClass
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//===----------------------------------------------------------------------===//
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CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
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: TheDef(R), Name(R->getName()), EnumValue(-1) {
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// Rename anonymous register classes.
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if (R->getName().size() > 9 && R->getName()[9] == '.') {
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static unsigned AnonCounter = 0;
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R->setName("AnonRegClass_"+utostr(AnonCounter++));
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}
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std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
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for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
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Record *Type = TypeList[i];
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if (!Type->isSubClassOf("ValueType"))
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throw "RegTypes list member '" + Type->getName() +
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"' does not derive from the ValueType class!";
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VTs.push_back(getValueType(Type));
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}
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assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
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// Allocation order 0 is the full set. AltOrders provides others.
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const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
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ListInit *AltOrders = R->getValueAsListInit("AltOrders");
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Orders.resize(1 + AltOrders->size());
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// Default allocation order always contains all registers.
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for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
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Orders[0].push_back((*Elements)[i]);
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Members.insert(RegBank.getReg((*Elements)[i]));
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}
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// Alternative allocation orders may be subsets.
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SetTheory::RecSet Order;
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for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
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RegBank.getSets().evaluate(AltOrders->getElement(i), Order);
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Orders[1 + i].append(Order.begin(), Order.end());
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// Verify that all altorder members are regclass members.
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while (!Order.empty()) {
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CodeGenRegister *Reg = RegBank.getReg(Order.back());
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Order.pop_back();
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if (!contains(Reg))
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throw TGError(R->getLoc(), " AltOrder register " + Reg->getName() +
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" is not a class member");
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}
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}
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// SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
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ListInit *SRC = R->getValueAsListInit("SubRegClasses");
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for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
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DagInit *DAG = dynamic_cast<DagInit*>(*i);
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if (!DAG) throw "SubRegClasses must contain DAGs";
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DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
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Record *RCRec;
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if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
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throw "Operator '" + DAG->getOperator()->getAsString() +
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"' in SubRegClasses is not a RegisterClass";
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// Iterate over args, all SubRegIndex instances.
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for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
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ai != ae; ++ai) {
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DefInit *Idx = dynamic_cast<DefInit*>(*ai);
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Record *IdxRec;
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if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
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throw "Argument '" + (*ai)->getAsString() +
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"' in SubRegClasses is not a SubRegIndex";
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if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
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throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
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}
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}
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// Allow targets to override the size in bits of the RegisterClass.
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unsigned Size = R->getValueAsInt("Size");
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Namespace = R->getValueAsString("Namespace");
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SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
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SpillAlignment = R->getValueAsInt("Alignment");
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CopyCost = R->getValueAsInt("CopyCost");
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Allocatable = R->getValueAsBit("isAllocatable");
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AltOrderSelect = R->getValueAsCode("AltOrderSelect");
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}
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// Create an inferred register class that was missing from the .td files.
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// Most properties will be inherited from the closest super-class after the
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// class structure has been computed.
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CodeGenRegisterClass::CodeGenRegisterClass(StringRef Name, Key Props)
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: Members(*Props.Members),
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TheDef(0),
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Name(Name),
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EnumValue(-1),
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SpillSize(Props.SpillSize),
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SpillAlignment(Props.SpillAlignment),
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CopyCost(0),
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Allocatable(true) {
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}
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// Compute inherited propertied for a synthesized register class.
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void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
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assert(!getDef() && "Only synthesized classes can inherit properties");
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assert(!SuperClasses.empty() && "Synthesized class without super class");
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// The last super-class is the smallest one.
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CodeGenRegisterClass &Super = *SuperClasses.back();
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// Most properties are copied directly.
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// Exceptions are members, size, and alignment
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Namespace = Super.Namespace;
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VTs = Super.VTs;
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CopyCost = Super.CopyCost;
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Allocatable = Super.Allocatable;
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AltOrderSelect = Super.AltOrderSelect;
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// Copy all allocation orders, filter out foreign registers from the larger
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// super-class.
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Orders.resize(Super.Orders.size());
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for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
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for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
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if (contains(RegBank.getReg(Super.Orders[i][j])))
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Orders[i].push_back(Super.Orders[i][j]);
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}
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bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
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return Members.count(Reg);
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}
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namespace llvm {
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raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
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OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment;
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for (CodeGenRegister::Set::const_iterator I = K.Members->begin(),
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E = K.Members->end(); I != E; ++I)
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OS << ", " << (*I)->getName();
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return OS << " }";
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}
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}
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// This is a simple lexicographical order that can be used to search for sets.
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// It is not the same as the topological order provided by TopoOrderRC.
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bool CodeGenRegisterClass::Key::
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operator<(const CodeGenRegisterClass::Key &B) const {
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assert(Members && B.Members);
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if (*Members != *B.Members)
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return *Members < *B.Members;
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if (SpillSize != B.SpillSize)
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return SpillSize < B.SpillSize;
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return SpillAlignment < B.SpillAlignment;
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}
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// Returns true if RC is a strict subclass.
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// RC is a sub-class of this class if it is a valid replacement for any
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// instruction operand where a register of this classis required. It must
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// satisfy these conditions:
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//
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// 1. All RC registers are also in this.
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// 2. The RC spill size must not be smaller than our spill size.
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// 3. RC spill alignment must be compatible with ours.
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//
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static bool testSubClass(const CodeGenRegisterClass *A,
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const CodeGenRegisterClass *B) {
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return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 &&
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A->SpillSize <= B->SpillSize &&
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std::includes(A->getMembers().begin(), A->getMembers().end(),
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B->getMembers().begin(), B->getMembers().end(),
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CodeGenRegister::Less());
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}
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/// Sorting predicate for register classes. This provides a topological
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/// ordering that arranges all register classes before their sub-classes.
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///
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/// Register classes with the same registers, spill size, and alignment form a
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/// clique. They will be ordered alphabetically.
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///
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static int TopoOrderRC(const void *PA, const void *PB) {
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const CodeGenRegisterClass *A = *(const CodeGenRegisterClass* const*)PA;
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const CodeGenRegisterClass *B = *(const CodeGenRegisterClass* const*)PB;
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if (A == B)
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return 0;
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// Order by descending set size. Note that the classes' allocation order may
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// not have been computed yet. The Members set is always vaild.
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if (A->getMembers().size() > B->getMembers().size())
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return -1;
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if (A->getMembers().size() < B->getMembers().size())
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return 1;
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// Order by ascending spill size.
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if (A->SpillSize < B->SpillSize)
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return -1;
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if (A->SpillSize > B->SpillSize)
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return 1;
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// Order by ascending spill alignment.
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if (A->SpillAlignment < B->SpillAlignment)
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return -1;
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if (A->SpillAlignment > B->SpillAlignment)
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return 1;
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// Finally order by name as a tie breaker.
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return A->getName() < B->getName();
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}
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std::string CodeGenRegisterClass::getQualifiedName() const {
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if (Namespace.empty())
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return getName();
|
|
else
|
|
return Namespace + "::" + getName();
|
|
}
|
|
|
|
// Compute sub-classes of all register classes.
|
|
// Assume the classes are ordered topologically.
|
|
void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
|
|
ArrayRef<CodeGenRegisterClass*> RegClasses = RegBank.getRegClasses();
|
|
|
|
// Visit backwards so sub-classes are seen first.
|
|
for (unsigned rci = RegClasses.size(); rci; --rci) {
|
|
CodeGenRegisterClass &RC = *RegClasses[rci - 1];
|
|
RC.SubClasses.resize(RegClasses.size());
|
|
RC.SubClasses.set(RC.EnumValue);
|
|
|
|
// Normally, all subclasses have IDs >= rci, unless RC is part of a clique.
|
|
for (unsigned s = rci; s != RegClasses.size(); ++s) {
|
|
if (RC.SubClasses.test(s))
|
|
continue;
|
|
CodeGenRegisterClass *SubRC = RegClasses[s];
|
|
if (!testSubClass(&RC, SubRC))
|
|
continue;
|
|
// SubRC is a sub-class. Grap all its sub-classes so we won't have to
|
|
// check them again.
|
|
RC.SubClasses |= SubRC->SubClasses;
|
|
}
|
|
|
|
// Sweep up missed clique members. They will be immediately preceeding RC.
|
|
for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s)
|
|
RC.SubClasses.set(s - 1);
|
|
}
|
|
|
|
// Compute the SuperClasses lists from the SubClasses vectors.
|
|
for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
|
|
const BitVector &SC = RegClasses[rci]->getSubClasses();
|
|
for (int s = SC.find_first(); s >= 0; s = SC.find_next(s)) {
|
|
if (unsigned(s) == rci)
|
|
continue;
|
|
RegClasses[s]->SuperClasses.push_back(RegClasses[rci]);
|
|
}
|
|
}
|
|
|
|
// With the class hierarchy in place, let synthesized register classes inherit
|
|
// properties from their closest super-class. The iteration order here can
|
|
// propagate properties down multiple levels.
|
|
for (unsigned rci = 0; rci != RegClasses.size(); ++rci)
|
|
if (!RegClasses[rci]->getDef())
|
|
RegClasses[rci]->inheritProperties(RegBank);
|
|
}
|
|
|
|
void
|
|
CodeGenRegisterClass::getSuperRegClasses(Record *SubIdx, BitVector &Out) const {
|
|
DenseMap<Record*, SmallPtrSet<CodeGenRegisterClass*, 8> >::const_iterator
|
|
FindI = SuperRegClasses.find(SubIdx);
|
|
if (FindI == SuperRegClasses.end())
|
|
return;
|
|
for (SmallPtrSet<CodeGenRegisterClass*, 8>::const_iterator I =
|
|
FindI->second.begin(), E = FindI->second.end(); I != E; ++I)
|
|
Out.set((*I)->EnumValue);
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// CodeGenRegBank
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
|
|
// Configure register Sets to understand register classes and tuples.
|
|
Sets.addFieldExpander("RegisterClass", "MemberList");
|
|
Sets.addExpander("RegisterTuples", new TupleExpander());
|
|
|
|
// Read in the user-defined (named) sub-register indices.
|
|
// More indices will be synthesized later.
|
|
SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
|
|
std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord());
|
|
NumNamedIndices = SubRegIndices.size();
|
|
|
|
// Read in the register definitions.
|
|
std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
|
|
std::sort(Regs.begin(), Regs.end(), LessRecord());
|
|
Registers.reserve(Regs.size());
|
|
// Assign the enumeration values.
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i)
|
|
getReg(Regs[i]);
|
|
|
|
// Expand tuples and number the new registers.
|
|
std::vector<Record*> Tups =
|
|
Records.getAllDerivedDefinitions("RegisterTuples");
|
|
for (unsigned i = 0, e = Tups.size(); i != e; ++i) {
|
|
const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]);
|
|
for (unsigned j = 0, je = TupRegs->size(); j != je; ++j)
|
|
getReg((*TupRegs)[j]);
|
|
}
|
|
|
|
// Precompute all sub-register maps now all the registers are known.
|
|
// This will create Composite entries for all inferred sub-register indices.
|
|
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
|
|
Registers[i]->getSubRegs(*this);
|
|
|
|
// Read in register class definitions.
|
|
std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
|
|
if (RCs.empty())
|
|
throw std::string("No 'RegisterClass' subclasses defined!");
|
|
|
|
// Allocate user-defined register classes.
|
|
RegClasses.reserve(RCs.size());
|
|
for (unsigned i = 0, e = RCs.size(); i != e; ++i)
|
|
addToMaps(new CodeGenRegisterClass(*this, RCs[i]));
|
|
|
|
// Infer missing classes to create a full algebra.
|
|
computeInferredRegisterClasses();
|
|
|
|
// Order register classes topologically and assign enum values.
|
|
array_pod_sort(RegClasses.begin(), RegClasses.end(), TopoOrderRC);
|
|
for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
|
|
RegClasses[i]->EnumValue = i;
|
|
CodeGenRegisterClass::computeSubClasses(*this);
|
|
}
|
|
|
|
CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
|
|
CodeGenRegister *&Reg = Def2Reg[Def];
|
|
if (Reg)
|
|
return Reg;
|
|
Reg = new CodeGenRegister(Def, Registers.size() + 1);
|
|
Registers.push_back(Reg);
|
|
return Reg;
|
|
}
|
|
|
|
void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) {
|
|
RegClasses.push_back(RC);
|
|
|
|
if (Record *Def = RC->getDef())
|
|
Def2RC.insert(std::make_pair(Def, RC));
|
|
|
|
// Duplicate classes are rejected by insert().
|
|
// That's OK, we only care about the properties handled by CGRC::Key.
|
|
CodeGenRegisterClass::Key K(*RC);
|
|
Key2RC.insert(std::make_pair(K, RC));
|
|
}
|
|
|
|
// Create a synthetic sub-class if it is missing.
|
|
CodeGenRegisterClass*
|
|
CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
|
|
const CodeGenRegister::Set *Members,
|
|
StringRef Name) {
|
|
// Synthetic sub-class has the same size and alignment as RC.
|
|
CodeGenRegisterClass::Key K(Members, RC->SpillSize, RC->SpillAlignment);
|
|
RCKeyMap::const_iterator FoundI = Key2RC.find(K);
|
|
if (FoundI != Key2RC.end())
|
|
return FoundI->second;
|
|
|
|
// Sub-class doesn't exist, create a new one.
|
|
CodeGenRegisterClass *NewRC = new CodeGenRegisterClass(Name, K);
|
|
addToMaps(NewRC);
|
|
return NewRC;
|
|
}
|
|
|
|
CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
|
|
if (CodeGenRegisterClass *RC = Def2RC[Def])
|
|
return RC;
|
|
|
|
throw TGError(Def->getLoc(), "Not a known RegisterClass!");
|
|
}
|
|
|
|
Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B,
|
|
bool create) {
|
|
// Look for an existing entry.
|
|
Record *&Comp = Composite[std::make_pair(A, B)];
|
|
if (Comp || !create)
|
|
return Comp;
|
|
|
|
// None exists, synthesize one.
|
|
std::string Name = A->getName() + "_then_" + B->getName();
|
|
Comp = new Record(Name, SMLoc(), Records);
|
|
SubRegIndices.push_back(Comp);
|
|
return Comp;
|
|
}
|
|
|
|
unsigned CodeGenRegBank::getSubRegIndexNo(Record *idx) {
|
|
std::vector<Record*>::const_iterator i =
|
|
std::find(SubRegIndices.begin(), SubRegIndices.end(), idx);
|
|
assert(i != SubRegIndices.end() && "Not a SubRegIndex");
|
|
return (i - SubRegIndices.begin()) + 1;
|
|
}
|
|
|
|
void CodeGenRegBank::computeComposites() {
|
|
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
|
|
CodeGenRegister *Reg1 = Registers[i];
|
|
const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
|
|
for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
|
|
e1 = SRM1.end(); i1 != e1; ++i1) {
|
|
Record *Idx1 = i1->first;
|
|
CodeGenRegister *Reg2 = i1->second;
|
|
// Ignore identity compositions.
|
|
if (Reg1 == Reg2)
|
|
continue;
|
|
const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
|
|
// Try composing Idx1 with another SubRegIndex.
|
|
for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
|
|
e2 = SRM2.end(); i2 != e2; ++i2) {
|
|
std::pair<Record*, Record*> IdxPair(Idx1, i2->first);
|
|
CodeGenRegister *Reg3 = i2->second;
|
|
// Ignore identity compositions.
|
|
if (Reg2 == Reg3)
|
|
continue;
|
|
// OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
|
|
for (CodeGenRegister::SubRegMap::const_iterator i1d = SRM1.begin(),
|
|
e1d = SRM1.end(); i1d != e1d; ++i1d) {
|
|
if (i1d->second == Reg3) {
|
|
std::pair<CompositeMap::iterator, bool> Ins =
|
|
Composite.insert(std::make_pair(IdxPair, i1d->first));
|
|
// Conflicting composition? Emit a warning but allow it.
|
|
if (!Ins.second && Ins.first->second != i1d->first) {
|
|
errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1)
|
|
<< " and " << getQualifiedName(IdxPair.second)
|
|
<< " compose ambiguously as "
|
|
<< getQualifiedName(Ins.first->second) << " or "
|
|
<< getQualifiedName(i1d->first) << "\n";
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
|
|
// compositions, so remove any mappings of that form.
|
|
for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
|
|
i != e;) {
|
|
CompositeMap::iterator j = i;
|
|
++i;
|
|
if (j->first.second == j->second)
|
|
Composite.erase(j);
|
|
}
|
|
}
|
|
|
|
// Compute sets of overlapping registers.
|
|
//
|
|
// The standard set is all super-registers and all sub-registers, but the
|
|
// target description can add arbitrary overlapping registers via the 'Aliases'
|
|
// field. This complicates things, but we can compute overlapping sets using
|
|
// the following rules:
|
|
//
|
|
// 1. The relation overlap(A, B) is reflexive and symmetric but not transitive.
|
|
//
|
|
// 2. overlap(A, B) implies overlap(A, S) for all S in supers(B).
|
|
//
|
|
// Alternatively:
|
|
//
|
|
// overlap(A, B) iff there exists:
|
|
// A' in { A, subregs(A) } and B' in { B, subregs(B) } such that:
|
|
// A' = B' or A' in aliases(B') or B' in aliases(A').
|
|
//
|
|
// Here subregs(A) is the full flattened sub-register set returned by
|
|
// A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the
|
|
// description of register A.
|
|
//
|
|
// This also implies that registers with a common sub-register are considered
|
|
// overlapping. This can happen when forming register pairs:
|
|
//
|
|
// P0 = (R0, R1)
|
|
// P1 = (R1, R2)
|
|
// P2 = (R2, R3)
|
|
//
|
|
// In this case, we will infer an overlap between P0 and P1 because of the
|
|
// shared sub-register R1. There is no overlap between P0 and P2.
|
|
//
|
|
void CodeGenRegBank::
|
|
computeOverlaps(std::map<const CodeGenRegister*, CodeGenRegister::Set> &Map) {
|
|
assert(Map.empty());
|
|
|
|
// Collect overlaps that don't follow from rule 2.
|
|
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
|
|
CodeGenRegister *Reg = Registers[i];
|
|
CodeGenRegister::Set &Overlaps = Map[Reg];
|
|
|
|
// Reg overlaps itself.
|
|
Overlaps.insert(Reg);
|
|
|
|
// All super-registers overlap.
|
|
const CodeGenRegister::SuperRegList &Supers = Reg->getSuperRegs();
|
|
Overlaps.insert(Supers.begin(), Supers.end());
|
|
|
|
// Form symmetrical relations from the special Aliases[] lists.
|
|
std::vector<Record*> RegList = Reg->TheDef->getValueAsListOfDefs("Aliases");
|
|
for (unsigned i2 = 0, e2 = RegList.size(); i2 != e2; ++i2) {
|
|
CodeGenRegister *Reg2 = getReg(RegList[i2]);
|
|
CodeGenRegister::Set &Overlaps2 = Map[Reg2];
|
|
const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs();
|
|
// Reg overlaps Reg2 which implies it overlaps supers(Reg2).
|
|
Overlaps.insert(Reg2);
|
|
Overlaps.insert(Supers2.begin(), Supers2.end());
|
|
Overlaps2.insert(Reg);
|
|
Overlaps2.insert(Supers.begin(), Supers.end());
|
|
}
|
|
}
|
|
|
|
// Apply rule 2. and inherit all sub-register overlaps.
|
|
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
|
|
CodeGenRegister *Reg = Registers[i];
|
|
CodeGenRegister::Set &Overlaps = Map[Reg];
|
|
const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
|
|
for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM.begin(),
|
|
e2 = SRM.end(); i2 != e2; ++i2) {
|
|
CodeGenRegister::Set &Overlaps2 = Map[i2->second];
|
|
Overlaps.insert(Overlaps2.begin(), Overlaps2.end());
|
|
}
|
|
}
|
|
}
|
|
|
|
void CodeGenRegBank::computeDerivedInfo() {
|
|
computeComposites();
|
|
}
|
|
|
|
//
|
|
// Synthesize missing register class intersections.
|
|
//
|
|
// Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
|
|
// returns a maximal register class for all X.
|
|
//
|
|
void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
|
|
for (unsigned rci = 0, rce = RegClasses.size(); rci != rce; ++rci) {
|
|
CodeGenRegisterClass *RC1 = RC;
|
|
CodeGenRegisterClass *RC2 = RegClasses[rci];
|
|
if (RC1 == RC2)
|
|
continue;
|
|
|
|
// Compute the set intersection of RC1 and RC2.
|
|
const CodeGenRegister::Set &Memb1 = RC1->getMembers();
|
|
const CodeGenRegister::Set &Memb2 = RC2->getMembers();
|
|
CodeGenRegister::Set Intersection;
|
|
std::set_intersection(Memb1.begin(), Memb1.end(),
|
|
Memb2.begin(), Memb2.end(),
|
|
std::inserter(Intersection, Intersection.begin()),
|
|
CodeGenRegister::Less());
|
|
|
|
// Skip disjoint class pairs.
|
|
if (Intersection.empty())
|
|
continue;
|
|
|
|
// If RC1 and RC2 have different spill sizes or alignments, use the
|
|
// larger size for sub-classing. If they are equal, prefer RC1.
|
|
if (RC2->SpillSize > RC1->SpillSize ||
|
|
(RC2->SpillSize == RC1->SpillSize &&
|
|
RC2->SpillAlignment > RC1->SpillAlignment))
|
|
std::swap(RC1, RC2);
|
|
|
|
getOrCreateSubClass(RC1, &Intersection,
|
|
RC1->getName() + "_and_" + RC2->getName());
|
|
}
|
|
}
|
|
|
|
//
|
|
// Synthesize missing sub-classes for getSubClassWithSubReg().
|
|
//
|
|
// Make sure that the set of registers in RC with a given SubIdx sub-register
|
|
// form a register class. Update RC->SubClassWithSubReg.
|
|
//
|
|
void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
|
|
// Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
|
|
typedef std::map<Record*, CodeGenRegister::Set, LessRecord> SubReg2SetMap;
|
|
|
|
// Compute the set of registers supporting each SubRegIndex.
|
|
SubReg2SetMap SRSets;
|
|
for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(),
|
|
RE = RC->getMembers().end(); RI != RE; ++RI) {
|
|
const CodeGenRegister::SubRegMap &SRM = (*RI)->getSubRegs();
|
|
for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
|
|
E = SRM.end(); I != E; ++I)
|
|
SRSets[I->first].insert(*RI);
|
|
}
|
|
|
|
// Find matching classes for all SRSets entries. Iterate in SubRegIndex
|
|
// numerical order to visit synthetic indices last.
|
|
for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
|
|
Record *SubIdx = SubRegIndices[sri];
|
|
SubReg2SetMap::const_iterator I = SRSets.find(SubIdx);
|
|
// Unsupported SubRegIndex. Skip it.
|
|
if (I == SRSets.end())
|
|
continue;
|
|
// In most cases, all RC registers support the SubRegIndex.
|
|
if (I->second.size() == RC->getMembers().size()) {
|
|
RC->setSubClassWithSubReg(SubIdx, RC);
|
|
continue;
|
|
}
|
|
// This is a real subset. See if we have a matching class.
|
|
CodeGenRegisterClass *SubRC =
|
|
getOrCreateSubClass(RC, &I->second,
|
|
RC->getName() + "_with_" + I->first->getName());
|
|
RC->setSubClassWithSubReg(SubIdx, SubRC);
|
|
}
|
|
}
|
|
|
|
//
|
|
// Synthesize missing sub-classes of RC for getMatchingSuperRegClass().
|
|
//
|
|
// Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X)
|
|
// has a maximal result for any SubIdx and any X >= FirstSubRegRC.
|
|
//
|
|
|
|
void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
|
|
unsigned FirstSubRegRC) {
|
|
SmallVector<std::pair<const CodeGenRegister*,
|
|
const CodeGenRegister*>, 16> SSPairs;
|
|
|
|
// Iterate in SubRegIndex numerical order to visit synthetic indices last.
|
|
for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
|
|
Record *SubIdx = SubRegIndices[sri];
|
|
// Skip indexes that aren't fully supported by RC's registers. This was
|
|
// computed by inferSubClassWithSubReg() above which should have been
|
|
// called first.
|
|
if (RC->getSubClassWithSubReg(SubIdx) != RC)
|
|
continue;
|
|
|
|
// Build list of (Super, Sub) pairs for this SubIdx.
|
|
SSPairs.clear();
|
|
for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(),
|
|
RE = RC->getMembers().end(); RI != RE; ++RI) {
|
|
const CodeGenRegister *Super = *RI;
|
|
const CodeGenRegister *Sub = Super->getSubRegs().find(SubIdx)->second;
|
|
assert(Sub && "Missing sub-register");
|
|
SSPairs.push_back(std::make_pair(Super, Sub));
|
|
}
|
|
|
|
// Iterate over sub-register class candidates. Ignore classes created by
|
|
// this loop. They will never be useful.
|
|
for (unsigned rci = FirstSubRegRC, rce = RegClasses.size(); rci != rce;
|
|
++rci) {
|
|
CodeGenRegisterClass *SubRC = RegClasses[rci];
|
|
// Compute the subset of RC that maps into SubRC.
|
|
CodeGenRegister::Set SubSet;
|
|
for (unsigned i = 0, e = SSPairs.size(); i != e; ++i)
|
|
if (SubRC->contains(SSPairs[i].second))
|
|
SubSet.insert(SSPairs[i].first);
|
|
if (SubSet.empty())
|
|
continue;
|
|
// RC injects completely into SubRC.
|
|
if (SubSet.size() == SSPairs.size()) {
|
|
SubRC->addSuperRegClass(SubIdx, RC);
|
|
continue;
|
|
}
|
|
// Only a subset of RC maps into SubRC. Make sure it is represented by a
|
|
// class.
|
|
getOrCreateSubClass(RC, &SubSet, RC->getName() +
|
|
"_with_" + SubIdx->getName() +
|
|
"_in_" + SubRC->getName());
|
|
}
|
|
}
|
|
}
|
|
|
|
|
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//
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// Infer missing register classes.
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//
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void CodeGenRegBank::computeInferredRegisterClasses() {
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// When this function is called, the register classes have not been sorted
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// and assigned EnumValues yet. That means getSubClasses(),
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// getSuperClasses(), and hasSubClass() functions are defunct.
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unsigned FirstNewRC = RegClasses.size();
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// Visit all register classes, including the ones being added by the loop.
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for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
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CodeGenRegisterClass *RC = RegClasses[rci];
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// Synthesize answers for getSubClassWithSubReg().
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inferSubClassWithSubReg(RC);
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// Synthesize answers for getCommonSubClass().
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inferCommonSubClass(RC);
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// Synthesize answers for getMatchingSuperRegClass().
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inferMatchingSuperRegClass(RC);
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// New register classes are created while this loop is running, and we need
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// to visit all of them. I particular, inferMatchingSuperRegClass needs
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// to match old super-register classes with sub-register classes created
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// after inferMatchingSuperRegClass was called. At this point,
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// inferMatchingSuperRegClass has checked SuperRC = [0..rci] with SubRC =
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// [0..FirstNewRC). We need to cover SubRC = [FirstNewRC..rci].
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if (rci + 1 == FirstNewRC) {
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unsigned NextNewRC = RegClasses.size();
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for (unsigned rci2 = 0; rci2 != FirstNewRC; ++rci2)
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inferMatchingSuperRegClass(RegClasses[rci2], FirstNewRC);
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FirstNewRC = NextNewRC;
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}
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}
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}
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/// getRegisterClassForRegister - Find the register class that contains the
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/// specified physical register. If the register is not in a register class,
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/// return null. If the register is in multiple classes, and the classes have a
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/// superset-subset relationship and the same set of types, return the
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/// superclass. Otherwise return null.
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const CodeGenRegisterClass*
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CodeGenRegBank::getRegClassForRegister(Record *R) {
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const CodeGenRegister *Reg = getReg(R);
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ArrayRef<CodeGenRegisterClass*> RCs = getRegClasses();
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const CodeGenRegisterClass *FoundRC = 0;
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for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = *RCs[i];
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if (!RC.contains(Reg))
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continue;
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// If this is the first class that contains the register,
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// make a note of it and go on to the next class.
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if (!FoundRC) {
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FoundRC = &RC;
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continue;
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}
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// If a register's classes have different types, return null.
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if (RC.getValueTypes() != FoundRC->getValueTypes())
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return 0;
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// Check to see if the previously found class that contains
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// the register is a subclass of the current class. If so,
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// prefer the superclass.
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if (RC.hasSubClass(FoundRC)) {
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FoundRC = &RC;
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continue;
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}
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// Check to see if the previously found class that contains
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// the register is a superclass of the current class. If so,
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// prefer the superclass.
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if (FoundRC->hasSubClass(&RC))
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continue;
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// Multiple classes, and neither is a superclass of the other.
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// Return null.
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return 0;
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}
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return FoundRC;
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}
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