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ab304c42c2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@673 91177308-0d34-0410-b5e6-96231b3b80d8
1090 lines
33 KiB
C++
1090 lines
33 KiB
C++
//===-- SparcInternals.h - Header file for Sparc backend ---------*- C++ -*--=//
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//
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// This file defines stuff that is to be private to the Sparc backend, but is
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// shared among different portions of the backend.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARC_INTERNALS_H
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#define SPARC_INTERNALS_H
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#include "SparcRegClassInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineInstrInfo.h"
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#include "llvm/Target/MachineSchedInfo.h"
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#include "llvm/CodeGen/RegClass.h"
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#include "llvm/Type.h"
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#include <sys/types.h>
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class UltraSparc;
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// OpCodeMask definitions for the Sparc V9
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//
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const OpCodeMask Immed = 0x00002000; // immed or reg operand?
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const OpCodeMask Annul = 0x20000000; // annul delay instr?
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const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
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enum SparcInstrSchedClass {
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SPARC_NONE, /* Instructions with no scheduling restrictions */
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SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
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SPARC_IEU0, /* Integer class IEU0 */
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SPARC_IEU1, /* Integer class IEU1 */
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SPARC_FPM, /* FP Multiply or Divide instructions */
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SPARC_FPA, /* All other FP instructions */
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SPARC_CTI, /* Control-transfer instructions */
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SPARC_LD, /* Load instructions */
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SPARC_ST, /* Store instructions */
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SPARC_SINGLE, /* Instructions that must issue by themselves */
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SPARC_INV, /* This should stay at the end for the next value */
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SPARC_NUM_SCHED_CLASSES = SPARC_INV
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};
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//---------------------------------------------------------------------------
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// enum SparcMachineOpCode.
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// const MachineInstrDescriptor SparcMachineInstrDesc[]
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//
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// Purpose:
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// Description of UltraSparc machine instructions.
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//
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//---------------------------------------------------------------------------
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enum SparcMachineOpCode {
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#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
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ENUM,
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#include "SparcInstr.def"
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// End-of-array marker
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INVALID_OPCODE,
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NUM_REAL_OPCODES = RETURN+1, // number of valid opcodes
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NUM_TOTAL_OPCODES = INVALID_OPCODE
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};
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// Array of machine instruction descriptions...
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extern const MachineInstrDescriptor SparcMachineInstrDesc[];
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//---------------------------------------------------------------------------
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// class UltraSparcInstrInfo
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//
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// Purpose:
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// Information about individual instructions.
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// Most information is stored in the SparcMachineInstrDesc array above.
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// Other information is computed on demand, and most such functions
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// default to member functions in base class MachineInstrInfo.
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//---------------------------------------------------------------------------
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class UltraSparcInstrInfo : public MachineInstrInfo {
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public:
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/*ctor*/ UltraSparcInstrInfo();
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virtual bool hasResultInterlock (MachineOpCode opCode)
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{
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// All UltraSPARC instructions have interlocks (note that delay slots
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// are not considered here).
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// However, instructions that use the result of an FCMP produce a
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// 9-cycle stall if they are issued less than 3 cycles after the FCMP.
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// Force the compiler to insert a software interlock (i.e., gap of
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// 2 other groups, including NOPs if necessary).
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return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
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}
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};
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class LiveRange;
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class UltraSparc;
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class UltraSparcRegInfo : public MachineRegInfo
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{
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private:
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// The actual register classes in the Sparc
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enum RegClassIDs {
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IntRegClassID,
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FloatRegClassID,
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IntCCRegClassID,
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FloatCCRegClassID
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};
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// Type of registers available in Sparc. There can be several reg types
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// in the same class. For instace, the float reg class has Single/Double
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// types
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enum RegTypes {
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IntRegType,
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FPSingleRegType,
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FPDoubleRegType,
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IntCCRegType,
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FloatCCRegType
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};
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// WARNING: If the above enum order must be changed, also modify
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// getRegisterClassOfValue method below since it assumes this particular
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// order for efficiency.
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// reverse pointer to get info about the ultra sparc machine
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const UltraSparc *const UltraSparcInfo;
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// Both int and float rguments can be passed in 6 int regs -
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// %o0 to %o5 (cannot be changed)
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unsigned const NumOfIntArgRegs;
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unsigned const NumOfFloatArgRegs;
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unsigned const InvalidRegNum;
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//void setCallArgColor(LiveRange *const LR, const unsigned RegNo) const;
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void setCallOrRetArgCol(LiveRange *const LR, const unsigned RegNo,
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const MachineInstr *MI,AddedInstrMapType &AIMap)const;
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MachineInstr * getCopy2RegMI(const Value *SrcVal, const unsigned Reg,
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unsigned RegClassID) const ;
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Value *getValue4ReturnAddr( const MachineInstr * MInst ) const ;
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int getRegType(const LiveRange *const LR) const {
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unsigned Typ;
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switch( (LR->getRegClass())->getID() ) {
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case IntRegClassID: return IntRegType;
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case FloatRegClassID:
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Typ = LR->getTypeID();
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if( Typ == Type::FloatTyID )
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return FPSingleRegType;
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else if( Typ == Type::DoubleTyID )
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return FPDoubleRegType;
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else assert(0 && "Unknown type in FloatRegClass");
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case IntCCRegClassID: return IntCCRegType;
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case FloatCCRegClassID: return FloatCCRegType ;
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default: assert( 0 && "Unknown reg class ID");
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}
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}
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int getRegType(const Value *const Val) const {
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unsigned Typ;
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switch( getRegClassIDOfValue(Val) ) {
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case IntRegClassID: return IntRegType;
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case FloatRegClassID:
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Typ = (Val->getType())->getPrimitiveID();
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if( Typ == Type::FloatTyID )
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return FPSingleRegType;
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else if( Typ == Type::DoubleTyID )
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return FPDoubleRegType;
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else assert(0 && "Unknown type in FloatRegClass");
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case IntCCRegClassID: return IntCCRegType;
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case FloatCCRegClassID: return FloatCCRegType ;
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default: assert( 0 && "Unknown reg class ID");
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}
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}
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MachineInstr * cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
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const int RegType) const;
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MachineInstr * cpValue2RegMI(Value * Val, const unsigned DestReg,
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const int RegType) const;
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public:
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UltraSparcRegInfo(const UltraSparc *const USI ) : UltraSparcInfo(USI),
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NumOfIntArgRegs(6),
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NumOfFloatArgRegs(32),
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InvalidRegNum(1000)
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{
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MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
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MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
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MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
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MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
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assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
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"32 Float regs are used for float arg passing");
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}
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// ***** TODO Delete
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~UltraSparcRegInfo(void) { } // empty destructor
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inline const UltraSparc & getUltraSparcInfo() const {
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return *UltraSparcInfo;
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}
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inline unsigned getRegClassIDOfValue (const Value *const Val,
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bool isCCReg = false) const {
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Type::PrimitiveID ty = (Val->getType())->getPrimitiveID();
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unsigned res;
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if( (ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
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(ty == Type::MethodTyID) || (ty == Type::PointerTyID) )
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res = IntRegClassID; // sparc int reg (ty=0: void)
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else if( ty <= Type::DoubleTyID)
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res = FloatRegClassID; // sparc float reg class
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else {
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cout << "TypeID: " << ty << endl;
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assert(0 && "Cannot resolve register class for type");
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}
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if(isCCReg)
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return res + 2; // corresponidng condition code regiser
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else
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return res;
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}
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// returns the register tha contains always zero
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// this is the unified register number
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inline int getZeroRegNum() const { return SparcIntRegOrder::g0; }
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// returns the reg used for pushing the address when a method is called.
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// This can be used for other purposes between calls
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unsigned getCallAddressReg() const { return SparcIntRegOrder::o7; }
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// and when we return from a method. It should be made sure that this
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// register contains the return value when a return instruction is reached.
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unsigned getReturnAddressReg() const { return SparcIntRegOrder::i7; }
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void suggestRegs4MethodArgs(const Method *const Meth,
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LiveRangeInfo& LRI) const;
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void suggestRegs4CallArgs(const CallInst *const CallI,
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LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
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void suggestReg4RetValue(const ReturnInst *const RetI,
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LiveRangeInfo& LRI) const;
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void colorMethodArgs(const Method *const Meth, LiveRangeInfo& LRI,
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AddedInstrns *const FirstAI) const;
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void colorCallArgs(const CallInst *const CallI, LiveRangeInfo& LRI,
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AddedInstrns *const CallAI) const;
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void colorRetValue(const ReturnInst *const RetI, LiveRangeInfo& LRI,
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AddedInstrns *const RetAI) const;
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bool handleSpecialMInstr(const MachineInstr * MInst,
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LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
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static void printReg(const LiveRange *const LR) ;
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// this method provides a unique number for each register
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inline int getUnifiedRegNum(int RegClassID, int reg) const {
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if( RegClassID == IntRegClassID && reg < 32 )
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return reg;
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else if ( RegClassID == FloatRegClassID && reg < 64)
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return reg + 32; // we have 32 int regs
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else if( RegClassID == FloatCCRegClassID && reg < 4)
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return reg + 32 + 64; // 32 int, 64 float
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else if( RegClassID == IntCCRegClassID )
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return 4+ 32 + 64; // only int cc reg
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else if (reg==1000) //****** TODO: Remove
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return 1000;
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else
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assert(0 && "Invalid register class or reg number");
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}
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// given the unified register number, this gives the name
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inline const string getUnifiedRegName(int reg) const {
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if( reg < 32 )
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return SparcIntRegOrder::getRegName(reg);
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else if ( reg < (64 + 32) )
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return SparcFloatRegOrder::getRegName( reg - 32);
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else if( reg < (64+32+4) )
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return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
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else if ( reg == 64+32+4)
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return "xcc"; // only integer cc reg
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else if (reg==1000) //****** TODO: Remove
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return "<*NoReg*>";
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else
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assert(0 && "Invalid register number");
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}
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};
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/*---------------------------------------------------------------------------
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Scheduling guidelines for SPARC IIi:
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I-Cache alignment rules (pg 326)
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-- Align a branch target instruction so that it's entire group is within
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the same cache line (may be 1-4 instructions).
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** Don't let a branch that is predicted taken be the last instruction
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on an I-cache line: delay slot will need an entire line to be fetched
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-- Make a FP instruction or a branch be the 4th instruction in a group.
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For branches, there are tradeoffs in reordering to make this happen
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(see pg. 327).
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** Don't put a branch in a group that crosses a 32-byte boundary!
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An artificial branch is inserted after every 32 bytes, and having
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another branch will force the group to be broken into 2 groups.
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iTLB rules:
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-- Don't let a loop span two memory pages, if possible
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Branch prediction performance:
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-- Don't make the branch in a delay slot the target of a branch
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-- Try not to have 2 predicted branches within a group of 4 instructions
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(because each such group has a single branch target field).
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-- Try to align branches in slots 0, 2, 4 or 6 of a cache line (to avoid
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the wrong prediction bits being used in some cases).
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D-Cache timing constraints:
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-- Signed int loads of less than 64 bits have 3 cycle latency, not 2
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-- All other loads that hit in D-Cache have 2 cycle latency
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-- All loads are returned IN ORDER, so a D-Cache miss will delay a later hit
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-- Mis-aligned loads or stores cause a trap. In particular, replace
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mis-aligned FP double precision l/s with 2 single-precision l/s.
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-- Simulations of integer codes show increase in avg. group size of
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33% when code (including esp. non-faulting loads) is moved across
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one branch, and 50% across 2 branches.
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E-Cache timing constraints:
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-- Scheduling for E-cache (D-Cache misses) is effective (due to load buffering)
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Store buffer timing constraints:
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-- Stores can be executed in same cycle as instruction producing the value
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-- Stores are buffered and have lower priority for E-cache until
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highwater mark is reached in the store buffer (5 stores)
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Pipeline constraints:
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-- Shifts can only use IEU0.
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-- CC setting instructions can only use IEU1.
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-- Several other instructions must only use IEU1:
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EDGE(?), ARRAY(?), CALL, JMPL, BPr, PST, and FCMP.
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-- Two instructions cannot store to the same register file in a single cycle
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(single write port per file).
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Issue and grouping constraints:
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-- FP and branch instructions must use slot 4.
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-- Shift instructions cannot be grouped with other IEU0-specific instructions.
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-- CC setting instructions cannot be grouped with other IEU1-specific instrs.
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-- Several instructions must be issued in a single-instruction group:
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MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
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-- A CALL or JMPL breaks a group, ie, is not combined with subsequent instrs.
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--
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--
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Branch delay slot scheduling rules:
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-- A CTI couple (two back-to-back CTI instructions in the dynamic stream)
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has a 9-instruction penalty: the entire pipeline is flushed when the
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second instruction reaches stage 9 (W-Writeback).
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-- Avoid putting multicycle instructions, and instructions that may cause
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load misses, in the delay slot of an annulling branch.
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-- Avoid putting WR, SAVE..., RESTORE and RETURN instructions in the
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delay slot of an annulling branch.
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*--------------------------------------------------------------------------- */
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//---------------------------------------------------------------------------
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// List of CPUResources for UltraSPARC IIi.
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//---------------------------------------------------------------------------
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const CPUResource AllIssueSlots( "All Instr Slots", 4);
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const CPUResource IntIssueSlots( "Int Instr Slots", 3);
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const CPUResource First3IssueSlots("Instr Slots 0-3", 3);
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const CPUResource LSIssueSlots( "Load-Store Instr Slot", 1);
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const CPUResource CTIIssueSlots( "Ctrl Transfer Instr Slot", 1);
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const CPUResource FPAIssueSlots( "Int Instr Slot 1", 1);
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const CPUResource FPMIssueSlots( "Int Instr Slot 1", 1);
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// IEUN instructions can use either Alu and should use IAluN.
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// IEU0 instructions must use Alu 1 and should use both IAluN and IAlu0.
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// IEU1 instructions must use Alu 2 and should use both IAluN and IAlu1.
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const CPUResource IAluN("Int ALU 1or2", 2);
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const CPUResource IAlu0("Int ALU 1", 1);
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const CPUResource IAlu1("Int ALU 2", 1);
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const CPUResource LSAluC1("Load/Store Unit Addr Cycle", 1);
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const CPUResource LSAluC2("Load/Store Unit Issue Cycle", 1);
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const CPUResource LdReturn("Load Return Unit", 1);
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const CPUResource FPMAluC1("FP Mul/Div Alu Cycle 1", 1);
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const CPUResource FPMAluC2("FP Mul/Div Alu Cycle 2", 1);
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const CPUResource FPMAluC3("FP Mul/Div Alu Cycle 3", 1);
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const CPUResource FPAAluC1("FP Other Alu Cycle 1", 1);
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const CPUResource FPAAluC2("FP Other Alu Cycle 2", 1);
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const CPUResource FPAAluC3("FP Other Alu Cycle 3", 1);
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const CPUResource IRegReadPorts("Int Reg ReadPorts", INT_MAX); // CHECK
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const CPUResource IRegWritePorts("Int Reg WritePorts", 2); // CHECK
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const CPUResource FPRegReadPorts("FP Reg Read Ports", INT_MAX); // CHECK
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const CPUResource FPRegWritePorts("FP Reg Write Ports", 1); // CHECK
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const CPUResource CTIDelayCycle( "CTI delay cycle", 1);
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const CPUResource FCMPDelayCycle("FCMP delay cycle", 1);
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//---------------------------------------------------------------------------
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// const InstrClassRUsage SparcRUsageDesc[]
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//
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// Purpose:
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// Resource usage information for instruction in each scheduling class.
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// The InstrRUsage Objects for individual classes are specified first.
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// Note that fetch and decode are decoupled from the execution pipelines
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// via an instr buffer, so they are not included in the cycles below.
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//---------------------------------------------------------------------------
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const InstrClassRUsage NoneClassRUsage = {
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SPARC_NONE,
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/*totCycles*/ 7,
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/* maxIssueNum */ 4,
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/* isSingleIssue */ false,
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/* breaksGroup */ false,
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/* numBubbles */ 0,
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/*numSlots*/ 4,
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/* feasibleSlots[] */ { 0, 1, 2, 3 },
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/*numEntries*/ 0,
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/* V[] */ {
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/*Cycle G */
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/*Cycle E */
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/*Cycle C */
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/*Cycle N1*/
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/*Cycle N1*/
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/*Cycle N1*/
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/*Cycle W */
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}
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};
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const InstrClassRUsage IEUNClassRUsage = {
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SPARC_IEUN,
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/*totCycles*/ 7,
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/* maxIssueNum */ 3,
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/* isSingleIssue */ false,
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/* breaksGroup */ false,
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/* numBubbles */ 0,
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/*numSlots*/ 3,
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/* feasibleSlots[] */ { 0, 1, 2 },
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/*numEntries*/ 4,
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/* V[] */ {
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/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
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{ IntIssueSlots.rid, 0, 1 },
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/*Cycle E */ { IAluN.rid, 1, 1 },
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/*Cycle C */
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle W */ { IRegWritePorts.rid, 6, 1 }
|
|
}
|
|
};
|
|
|
|
const InstrClassRUsage IEU0ClassRUsage = {
|
|
SPARC_IEU0,
|
|
/*totCycles*/ 7,
|
|
|
|
/* maxIssueNum */ 1,
|
|
/* isSingleIssue */ false,
|
|
/* breaksGroup */ false,
|
|
/* numBubbles */ 0,
|
|
|
|
/*numSlots*/ 3,
|
|
/* feasibleSlots[] */ { 0, 1, 2 },
|
|
|
|
/*numEntries*/ 5,
|
|
/* V[] */ {
|
|
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
|
|
{ IntIssueSlots.rid, 0, 1 },
|
|
/*Cycle E */ { IAluN.rid, 1, 1 },
|
|
{ IAlu0.rid, 1, 1 },
|
|
/*Cycle C */
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle W */ { IRegWritePorts.rid, 6, 1 }
|
|
}
|
|
};
|
|
|
|
const InstrClassRUsage IEU1ClassRUsage = {
|
|
SPARC_IEU1,
|
|
/*totCycles*/ 7,
|
|
|
|
/* maxIssueNum */ 1,
|
|
/* isSingleIssue */ false,
|
|
/* breaksGroup */ false,
|
|
/* numBubbles */ 0,
|
|
|
|
/*numSlots*/ 3,
|
|
/* feasibleSlots[] */ { 0, 1, 2 },
|
|
|
|
/*numEntries*/ 5,
|
|
/* V[] */ {
|
|
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
|
|
{ IntIssueSlots.rid, 0, 1 },
|
|
/*Cycle E */ { IAluN.rid, 1, 1 },
|
|
{ IAlu1.rid, 1, 1 },
|
|
/*Cycle C */
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle W */ { IRegWritePorts.rid, 6, 1 }
|
|
}
|
|
};
|
|
|
|
const InstrClassRUsage FPMClassRUsage = {
|
|
SPARC_FPM,
|
|
/*totCycles*/ 7,
|
|
|
|
/* maxIssueNum */ 1,
|
|
/* isSingleIssue */ false,
|
|
/* breaksGroup */ false,
|
|
/* numBubbles */ 0,
|
|
|
|
/*numSlots*/ 4,
|
|
/* feasibleSlots[] */ { 0, 1, 2, 3 },
|
|
|
|
/*numEntries*/ 7,
|
|
/* V[] */ {
|
|
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
|
|
{ FPMIssueSlots.rid, 0, 1 },
|
|
/*Cycle E */ { FPRegReadPorts.rid, 1, 1 },
|
|
/*Cycle C */ { FPMAluC1.rid, 2, 1 },
|
|
/*Cycle N1*/ { FPMAluC2.rid, 3, 1 },
|
|
/*Cycle N1*/ { FPMAluC3.rid, 4, 1 },
|
|
/*Cycle N1*/
|
|
/*Cycle W */ { FPRegWritePorts.rid, 6, 1 }
|
|
}
|
|
};
|
|
|
|
const InstrClassRUsage FPAClassRUsage = {
|
|
SPARC_FPA,
|
|
/*totCycles*/ 7,
|
|
|
|
/* maxIssueNum */ 1,
|
|
/* isSingleIssue */ false,
|
|
/* breaksGroup */ false,
|
|
/* numBubbles */ 0,
|
|
|
|
/*numSlots*/ 4,
|
|
/* feasibleSlots[] */ { 0, 1, 2, 3 },
|
|
|
|
/*numEntries*/ 7,
|
|
/* V[] */ {
|
|
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
|
|
{ FPAIssueSlots.rid, 0, 1 },
|
|
/*Cycle E */ { FPRegReadPorts.rid, 1, 1 },
|
|
/*Cycle C */ { FPAAluC1.rid, 2, 1 },
|
|
/*Cycle N1*/ { FPAAluC2.rid, 3, 1 },
|
|
/*Cycle N1*/ { FPAAluC3.rid, 4, 1 },
|
|
/*Cycle N1*/
|
|
/*Cycle W */ { FPRegWritePorts.rid, 6, 1 }
|
|
}
|
|
};
|
|
|
|
const InstrClassRUsage LDClassRUsage = {
|
|
SPARC_LD,
|
|
/*totCycles*/ 7,
|
|
|
|
/* maxIssueNum */ 1,
|
|
/* isSingleIssue */ false,
|
|
/* breaksGroup */ false,
|
|
/* numBubbles */ 0,
|
|
|
|
/*numSlots*/ 3,
|
|
/* feasibleSlots[] */ { 0, 1, 2, },
|
|
|
|
/*numEntries*/ 6,
|
|
/* V[] */ {
|
|
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
|
|
{ First3IssueSlots.rid, 0, 1 },
|
|
{ LSIssueSlots.rid, 0, 1 },
|
|
/*Cycle E */ { LSAluC1.rid, 1, 1 },
|
|
/*Cycle C */ { LSAluC2.rid, 2, 1 },
|
|
{ LdReturn.rid, 2, 1 },
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle W */ { IRegWritePorts.rid, 6, 1 }
|
|
}
|
|
};
|
|
|
|
const InstrClassRUsage STClassRUsage = {
|
|
SPARC_ST,
|
|
/*totCycles*/ 7,
|
|
|
|
/* maxIssueNum */ 1,
|
|
/* isSingleIssue */ false,
|
|
/* breaksGroup */ false,
|
|
/* numBubbles */ 0,
|
|
|
|
/*numSlots*/ 3,
|
|
/* feasibleSlots[] */ { 0, 1, 2 },
|
|
|
|
/*numEntries*/ 4,
|
|
/* V[] */ {
|
|
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
|
|
{ First3IssueSlots.rid, 0, 1 },
|
|
{ LSIssueSlots.rid, 0, 1 },
|
|
/*Cycle E */ { LSAluC1.rid, 1, 1 },
|
|
/*Cycle C */ { LSAluC2.rid, 2, 1 }
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle W */
|
|
}
|
|
};
|
|
|
|
const InstrClassRUsage CTIClassRUsage = {
|
|
SPARC_CTI,
|
|
/*totCycles*/ 7,
|
|
|
|
/* maxIssueNum */ 1,
|
|
/* isSingleIssue */ false,
|
|
/* breaksGroup */ false,
|
|
/* numBubbles */ 0,
|
|
|
|
/*numSlots*/ 4,
|
|
/* feasibleSlots[] */ { 0, 1, 2, 3 },
|
|
|
|
/*numEntries*/ 4,
|
|
/* V[] */ {
|
|
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
|
|
{ CTIIssueSlots.rid, 0, 1 },
|
|
/*Cycle E */ { IAlu0.rid, 1, 1 },
|
|
/*Cycles E-C */ { CTIDelayCycle.rid, 1, 2 }
|
|
/*Cycle C */
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle W */
|
|
}
|
|
};
|
|
|
|
const InstrClassRUsage SingleClassRUsage = {
|
|
SPARC_SINGLE,
|
|
/*totCycles*/ 7,
|
|
|
|
/* maxIssueNum */ 1,
|
|
/* isSingleIssue */ true,
|
|
/* breaksGroup */ false,
|
|
/* numBubbles */ 0,
|
|
|
|
/*numSlots*/ 1,
|
|
/* feasibleSlots[] */ { 0 },
|
|
|
|
/*numEntries*/ 5,
|
|
/* V[] */ {
|
|
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
|
|
{ AllIssueSlots.rid, 0, 1 },
|
|
{ AllIssueSlots.rid, 0, 1 },
|
|
{ AllIssueSlots.rid, 0, 1 },
|
|
/*Cycle E */ { IAlu0.rid, 1, 1 }
|
|
/*Cycle C */
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle N1*/
|
|
/*Cycle W */
|
|
}
|
|
};
|
|
|
|
|
|
const InstrClassRUsage SparcRUsageDesc[] = {
|
|
NoneClassRUsage,
|
|
IEUNClassRUsage,
|
|
IEU0ClassRUsage,
|
|
IEU1ClassRUsage,
|
|
FPMClassRUsage,
|
|
FPAClassRUsage,
|
|
CTIClassRUsage,
|
|
LDClassRUsage,
|
|
STClassRUsage,
|
|
SingleClassRUsage
|
|
};
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// const InstrIssueDelta SparcInstrIssueDeltas[]
|
|
//
|
|
// Purpose:
|
|
// Changes to issue restrictions information in InstrClassRUsage for
|
|
// instructions that differ from other instructions in their class.
|
|
//---------------------------------------------------------------------------
|
|
|
|
const InstrIssueDelta SparcInstrIssueDeltas[] = {
|
|
|
|
// opCode, isSingleIssue, breaksGroup, numBubbles
|
|
|
|
// Special cases for single-issue only
|
|
// Other single issue cases are below.
|
|
//{ LDDA, true, true, 0 },
|
|
//{ STDA, true, true, 0 },
|
|
//{ LDDF, true, true, 0 },
|
|
//{ LDDFA, true, true, 0 },
|
|
{ ADDC, true, true, 0 },
|
|
{ ADDCcc, true, true, 0 },
|
|
{ SUBC, true, true, 0 },
|
|
{ SUBCcc, true, true, 0 },
|
|
//{ SAVE, true, true, 0 },
|
|
//{ RESTORE, true, true, 0 },
|
|
//{ LDSTUB, true, true, 0 },
|
|
//{ SWAP, true, true, 0 },
|
|
//{ SWAPA, true, true, 0 },
|
|
//{ CAS, true, true, 0 },
|
|
//{ CASA, true, true, 0 },
|
|
//{ CASX, true, true, 0 },
|
|
//{ CASXA, true, true, 0 },
|
|
//{ LDFSR, true, true, 0 },
|
|
//{ LDFSRA, true, true, 0 },
|
|
//{ LDXFSR, true, true, 0 },
|
|
//{ LDXFSRA, true, true, 0 },
|
|
//{ STFSR, true, true, 0 },
|
|
//{ STFSRA, true, true, 0 },
|
|
//{ STXFSR, true, true, 0 },
|
|
//{ STXFSRA, true, true, 0 },
|
|
//{ SAVED, true, true, 0 },
|
|
//{ RESTORED, true, true, 0 },
|
|
//{ FLUSH, true, true, 9 },
|
|
//{ FLUSHW, true, true, 9 },
|
|
//{ ALIGNADDR, true, true, 0 },
|
|
{ RETURN, true, true, 0 },
|
|
//{ DONE, true, true, 0 },
|
|
//{ RETRY, true, true, 0 },
|
|
//{ WR, true, true, 0 },
|
|
//{ WRPR, true, true, 4 },
|
|
//{ RD, true, true, 0 },
|
|
//{ RDPR, true, true, 0 },
|
|
//{ TCC, true, true, 0 },
|
|
//{ SHUTDOWN, true, true, 0 },
|
|
|
|
// Special cases for breaking group *before*
|
|
// CURRENTLY NOT SUPPORTED!
|
|
{ CALL, false, false, 0 },
|
|
{ JMPL, false, false, 0 },
|
|
|
|
// Special cases for breaking the group *after*
|
|
{ MULX, true, true, (4+34)/2 },
|
|
{ FDIVS, false, true, 0 },
|
|
{ FDIVD, false, true, 0 },
|
|
{ FDIVQ, false, true, 0 },
|
|
{ FSQRTS, false, true, 0 },
|
|
{ FSQRTD, false, true, 0 },
|
|
{ FSQRTQ, false, true, 0 },
|
|
//{ FCMP{LE,GT,NE,EQ}, false, true, 0 },
|
|
|
|
// Instructions that introduce bubbles
|
|
//{ MULScc, true, true, 2 },
|
|
//{ SMULcc, true, true, (4+18)/2 },
|
|
//{ UMULcc, true, true, (4+19)/2 },
|
|
{ SDIVX, true, true, 68 },
|
|
{ UDIVX, true, true, 68 },
|
|
//{ SDIVcc, true, true, 36 },
|
|
//{ UDIVcc, true, true, 37 },
|
|
//{ WR, false, false, 4 },
|
|
//{ WRPR, false, false, 4 },
|
|
};
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// const InstrRUsageDelta SparcInstrUsageDeltas[]
|
|
//
|
|
// Purpose:
|
|
// Changes to resource usage information in InstrClassRUsage for
|
|
// instructions that differ from other instructions in their class.
|
|
//---------------------------------------------------------------------------
|
|
|
|
const InstrRUsageDelta SparcInstrUsageDeltas[] = {
|
|
|
|
// MachineOpCode, Resource, Start cycle, Num cycles
|
|
|
|
//
|
|
// JMPL counts as a load/store instruction for issue!
|
|
//
|
|
{ JMPL, LSIssueSlots.rid, 0, 1 },
|
|
|
|
//
|
|
// Many instructions cannot issue for the next 2 cycles after an FCMP
|
|
// We model that with a fake resource FCMPDelayCycle.
|
|
//
|
|
{ FCMPS, FCMPDelayCycle.rid, 1, 3 },
|
|
{ FCMPD, FCMPDelayCycle.rid, 1, 3 },
|
|
{ FCMPQ, FCMPDelayCycle.rid, 1, 3 },
|
|
|
|
{ MULX, FCMPDelayCycle.rid, 1, 1 },
|
|
{ SDIVX, FCMPDelayCycle.rid, 1, 1 },
|
|
{ UDIVX, FCMPDelayCycle.rid, 1, 1 },
|
|
//{ SMULcc, FCMPDelayCycle.rid, 1, 1 },
|
|
//{ UMULcc, FCMPDelayCycle.rid, 1, 1 },
|
|
//{ SDIVcc, FCMPDelayCycle.rid, 1, 1 },
|
|
//{ UDIVcc, FCMPDelayCycle.rid, 1, 1 },
|
|
{ STD, FCMPDelayCycle.rid, 1, 1 },
|
|
{ FMOVRSZ, FCMPDelayCycle.rid, 1, 1 },
|
|
{ FMOVRSLEZ,FCMPDelayCycle.rid, 1, 1 },
|
|
{ FMOVRSLZ, FCMPDelayCycle.rid, 1, 1 },
|
|
{ FMOVRSNZ, FCMPDelayCycle.rid, 1, 1 },
|
|
{ FMOVRSGZ, FCMPDelayCycle.rid, 1, 1 },
|
|
{ FMOVRSGEZ,FCMPDelayCycle.rid, 1, 1 },
|
|
|
|
//
|
|
// Some instructions are stalled in the GROUP stage if a CTI is in
|
|
// the E or C stage
|
|
//
|
|
{ LDD, CTIDelayCycle.rid, 1, 1 },
|
|
//{ LDDA, CTIDelayCycle.rid, 1, 1 },
|
|
//{ LDDSTUB, CTIDelayCycle.rid, 1, 1 },
|
|
//{ LDDSTUBA, CTIDelayCycle.rid, 1, 1 },
|
|
//{ SWAP, CTIDelayCycle.rid, 1, 1 },
|
|
//{ SWAPA, CTIDelayCycle.rid, 1, 1 },
|
|
//{ CAS, CTIDelayCycle.rid, 1, 1 },
|
|
//{ CASA, CTIDelayCycle.rid, 1, 1 },
|
|
//{ CASX, CTIDelayCycle.rid, 1, 1 },
|
|
//{ CASXA, CTIDelayCycle.rid, 1, 1 },
|
|
|
|
//
|
|
// Signed int loads of less than dword size return data in cycle N1 (not C)
|
|
// and put all loads in consecutive cycles into delayed load return mode.
|
|
//
|
|
{ LDSB, LdReturn.rid, 2, -1 },
|
|
{ LDSB, LdReturn.rid, 3, 1 },
|
|
|
|
{ LDSH, LdReturn.rid, 2, -1 },
|
|
{ LDSH, LdReturn.rid, 3, 1 },
|
|
|
|
{ LDSW, LdReturn.rid, 2, -1 },
|
|
{ LDSW, LdReturn.rid, 3, 1 },
|
|
|
|
|
|
#undef EXPLICIT_BUBBLES_NEEDED
|
|
#ifdef EXPLICIT_BUBBLES_NEEDED
|
|
//
|
|
// MULScc inserts one bubble.
|
|
// This means it breaks the current group (captured in UltraSparcSchedInfo)
|
|
// *and occupies all issue slots for the next cycle
|
|
//
|
|
//{ MULScc, AllIssueSlots.rid, 2, 2-1 },
|
|
//{ MULScc, AllIssueSlots.rid, 2, 2-1 },
|
|
//{ MULScc, AllIssueSlots.rid, 2, 2-1 },
|
|
//{ MULScc, AllIssueSlots.rid, 2, 2-1 },
|
|
|
|
//
|
|
// SMULcc inserts between 4 and 18 bubbles, depending on #leading 0s in rs1.
|
|
// We just model this with a simple average.
|
|
//
|
|
//{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
|
|
//{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
|
|
//{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
|
|
//{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
|
|
|
|
// SMULcc inserts between 4 and 19 bubbles, depending on #leading 0s in rs1.
|
|
//{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
|
|
//{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
|
|
//{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
|
|
//{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
|
|
|
|
//
|
|
// MULX inserts between 4 and 34 bubbles, depending on #leading 0s in rs1.
|
|
//
|
|
{ MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
|
|
{ MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
|
|
{ MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
|
|
{ MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
|
|
|
|
//
|
|
// SDIVcc inserts 36 bubbles.
|
|
//
|
|
//{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
|
|
//{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
|
|
//{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
|
|
//{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
|
|
|
|
// UDIVcc inserts 37 bubbles.
|
|
//{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
|
|
//{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
|
|
//{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
|
|
//{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
|
|
|
|
//
|
|
// SDIVX inserts 68 bubbles.
|
|
//
|
|
{ SDIVX, AllIssueSlots.rid, 2, 68-1 },
|
|
{ SDIVX, AllIssueSlots.rid, 2, 68-1 },
|
|
{ SDIVX, AllIssueSlots.rid, 2, 68-1 },
|
|
{ SDIVX, AllIssueSlots.rid, 2, 68-1 },
|
|
|
|
//
|
|
// UDIVX inserts 68 bubbles.
|
|
//
|
|
{ UDIVX, AllIssueSlots.rid, 2, 68-1 },
|
|
{ UDIVX, AllIssueSlots.rid, 2, 68-1 },
|
|
{ UDIVX, AllIssueSlots.rid, 2, 68-1 },
|
|
{ UDIVX, AllIssueSlots.rid, 2, 68-1 },
|
|
|
|
//
|
|
// WR inserts 4 bubbles.
|
|
//
|
|
//{ WR, AllIssueSlots.rid, 2, 68-1 },
|
|
//{ WR, AllIssueSlots.rid, 2, 68-1 },
|
|
//{ WR, AllIssueSlots.rid, 2, 68-1 },
|
|
//{ WR, AllIssueSlots.rid, 2, 68-1 },
|
|
|
|
//
|
|
// WRPR inserts 4 bubbles.
|
|
//
|
|
//{ WRPR, AllIssueSlots.rid, 2, 68-1 },
|
|
//{ WRPR, AllIssueSlots.rid, 2, 68-1 },
|
|
//{ WRPR, AllIssueSlots.rid, 2, 68-1 },
|
|
//{ WRPR, AllIssueSlots.rid, 2, 68-1 },
|
|
|
|
//
|
|
// DONE inserts 9 bubbles.
|
|
//
|
|
//{ DONE, AllIssueSlots.rid, 2, 9-1 },
|
|
//{ DONE, AllIssueSlots.rid, 2, 9-1 },
|
|
//{ DONE, AllIssueSlots.rid, 2, 9-1 },
|
|
//{ DONE, AllIssueSlots.rid, 2, 9-1 },
|
|
|
|
//
|
|
// RETRY inserts 9 bubbles.
|
|
//
|
|
//{ RETRY, AllIssueSlots.rid, 2, 9-1 },
|
|
//{ RETRY, AllIssueSlots.rid, 2, 9-1 },
|
|
//{ RETRY, AllIssueSlots.rid, 2, 9-1 },
|
|
//{ RETRY, AllIssueSlots.rid, 2, 9-1 },
|
|
|
|
#endif EXPLICIT_BUBBLES_NEEDED
|
|
};
|
|
|
|
|
|
|
|
// Additional delays to be captured in code:
|
|
// 1. RDPR from several state registers (page 349)
|
|
// 2. RD from *any* register (page 349)
|
|
// 3. Writes to TICK, PSTATE, TL registers and FLUSH{W} instr (page 349)
|
|
// 4. Integer store can be in same group as instr producing value to store.
|
|
// 5. BICC and BPICC can be in the same group as instr producing CC (pg 350)
|
|
// 6. FMOVr cannot be in the same or next group as an IEU instr (pg 351).
|
|
// 7. The second instr. of a CTI group inserts 9 bubbles (pg 351)
|
|
// 8. WR{PR}, SVAE, SAVED, RESTORE, RESTORED, RETURN, RETRY, and DONE that
|
|
// follow an annulling branch cannot be issued in the same group or in
|
|
// the 3 groups following the branch.
|
|
// 9. A predicted annulled load does not stall dependent instructions.
|
|
// Other annulled delay slot instructions *do* stall dependents, so
|
|
// nothing special needs to be done for them during scheduling.
|
|
//10. Do not put a load use that may be annulled in the same group as the
|
|
// branch. The group will stall until the load returns.
|
|
//11. Single-prec. FP loads lock 2 registers, for dependency checking.
|
|
//
|
|
//
|
|
// Additional delays we cannot or will not capture:
|
|
// 1. If DCTI is last word of cache line, it is delayed until next line can be
|
|
// fetched. Also, other DCTI alignment-related delays (pg 352)
|
|
// 2. Load-after-store is delayed by 7 extra cycles if load hits in D-Cache.
|
|
// Also, several other store-load and load-store conflicts (pg 358)
|
|
// 3. MEMBAR, LD{X}FSR, LDD{A} and a bunch of other load stalls (pg 358)
|
|
// 4. There can be at most 8 outstanding buffered store instructions
|
|
// (including some others like MEMBAR, LDSTUB, CAS{AX}, and FLUSH)
|
|
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// class UltraSparcSchedInfo
|
|
//
|
|
// Purpose:
|
|
// Interface to instruction scheduling information for UltraSPARC.
|
|
// The parameter values above are based on UltraSPARC IIi.
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
|
class UltraSparcSchedInfo: public MachineSchedInfo {
|
|
public:
|
|
/*ctor*/ UltraSparcSchedInfo (const MachineInstrInfo* mii);
|
|
/*dtor*/ virtual ~UltraSparcSchedInfo () {}
|
|
protected:
|
|
virtual void initializeResources ();
|
|
};
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// class UltraSparcMachine
|
|
//
|
|
// Purpose:
|
|
// Primary interface to machine description for the UltraSPARC.
|
|
// Primarily just initializes machine-dependent parameters in
|
|
// class TargetMachine, and creates machine-dependent subclasses
|
|
// for classes such as InstrInfo, SchedInfo and RegInfo.
|
|
//---------------------------------------------------------------------------
|
|
|
|
class UltraSparc : public TargetMachine {
|
|
private:
|
|
UltraSparcInstrInfo instrInfo;
|
|
UltraSparcSchedInfo schedInfo;
|
|
UltraSparcRegInfo regInfo;
|
|
public:
|
|
UltraSparc();
|
|
virtual ~UltraSparc() {}
|
|
|
|
virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
|
|
virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
|
|
virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
|
|
|
|
// compileMethod - For the sparc, we do instruction selection, followed by
|
|
// delay slot scheduling, then register allocation.
|
|
//
|
|
virtual bool compileMethod(Method *M);
|
|
|
|
//
|
|
// emitAssembly - Output assembly language code (a .s file) for the specified
|
|
// module. The specified module must have been compiled before this may be
|
|
// used.
|
|
//
|
|
virtual void emitAssembly(const Module *M, ostream &OutStr);
|
|
};
|
|
|
|
|
|
#endif
|