mirror of
https://github.com/c64scene-ar/llvm-6502.git
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c01810eeb7
Without this hook, functions w/ a completely empty body (including no
epilogue) will cause an MCEmitter assertion failure.
For example,
define internal fastcc void @empty_function() {
unreachable
}
rdar://10947471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151673 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
1.4 KiB
C++
48 lines
1.4 KiB
C++
//===-- ARMInstrInfo.h - ARM Instruction Information ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMINSTRUCTIONINFO_H
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#define ARMINSTRUCTIONINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMRegisterInfo.h"
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#include "ARMSubtarget.h"
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#include "ARM.h"
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namespace llvm {
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class ARMSubtarget;
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class ARMInstrInfo : public ARMBaseInstrInfo {
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ARMRegisterInfo RI;
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public:
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explicit ARMInstrInfo(const ARMSubtarget &STI);
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/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
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void getNoopForMachoTarget(MCInst &NopInst) const;
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// Return the non-pre/post incrementing version of 'Opc'. Return 0
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// if there is not such an opcode.
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unsigned getUnindexedOpcode(unsigned Opc) const;
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const ARMRegisterInfo &getRegisterInfo() const { return RI; }
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};
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}
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#endif
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